5 Commits (9ca5ae07b27d78f2797e560674874f571a4470e7)

Author	SHA1	Message	Date
Iacob_Liviu	30b491fff7	tb: jesd204: update and automate frame_align_tb ... Fix jesd204 frame_aligh_tb by adding a fifo to solve rx and tx delay. It saves the data from tx and compares it with the recieved ones from rx.	2021-07-12 10:30:49 +01:00
stefan.raus	37238916df	Testbenches: Unify and optimize HDL testbenches ... Create a common 'run_tb.sh' script to be called by every testbench. Unify file and testbenches names. Fix util_pack/cpack_tb. Add parameters '-batch' and '-gui' for modelsim and xsim simulators (default is gui) Add ascript for that generates output in xml format (used by CI tools).	2021-05-07 19:53:14 +03:00
Laszlo Nagy	94181206c2	jesd204/tb: Update testbenches	2021-02-05 15:24:15 +02:00
Matt Blanton	400c3927f7	jesd204: Add support for 8-byte JESD204B, frame alignment character insertion/replacement ... Add support to JESD204 RX and TX core for 8-byte 8b/10b link mode, and frame alignment character replace/insert with or without scrambling. Add support for xcelium simulator to jesd204/tb Increased cores minor version.	2021-02-05 15:24:15 +02:00
Matt Blanton	1e04b2e2f2	jesd204_rx: Add RX frame alignment character check ... Add support for RX frame alignment character checking when scrambling is enabled and for link reset on misalignment. Add support for xcelium simulator to jesd204/tb	2020-07-31 11:43:41 +03:00