Commit Graph

56 Commits (9cb84456ee6cccf97088fced8394ae51c2a36229)

Author SHA1 Message Date
Istvan Csomortani bfa17844ff ad_serdes_in: General update
Added a parameter for option SDR / DDR mode, added a parameter for parallel data width.
Note: default IF_TYPE is SDR and default PARALLEL_WIDTH is 8
2014-10-07 17:42:27 +03:00
Istvan Csomortani 6a09a1ed19 ad9434: Fix the processor read interface
Fix the processor read interface, preventing to have nets with multiple drivers. Made a few cosmetic changes in the code too.
2014-09-25 16:51:58 +03:00
Istvan Csomortani ccb0b135ca ad9434: Fix the adc to dma interface.
All the device2dma interfaces needs to have a generic form : (data, enable, valid)/channel
2014-09-25 16:50:09 +03:00
Istvan Csomortani d5f4991e26 ad9434: Merge the ad9434_if interface data outputs into one single bus 2014-09-25 16:45:12 +03:00
Istvan Csomortani 079ed0ffb3 ad_serdes_in: Update the serdes_in module
Add additional IDELAY block before the ISERDES. Delet the IDDR blocks. Be aware, the ISERDES block are running in DDR mode. If the interface is SDR the maximum parallel data width is 4.
2014-09-25 16:40:29 +03:00
Istvan Csomortani 683561b67d AD9434: Initial check in of the library and project with ZC706 2014-09-24 18:27:17 +03:00