Commit Graph

3874 Commits (9cb84456ee6cccf97088fced8394ae51c2a36229)

Author SHA1 Message Date
Lars-Peter Clausen e033d6c48e m2k: Refresh Makefile
The util_cpack core is currently not used by the M2K project. Refresh the
Makefiles to reflect this.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-05-19 15:33:26 +02:00
Rejeesh Kutty 393577c911 util_adxcvr- 2016.4 gthe4 updates 2017-05-18 14:49:18 -04:00
Rejeesh Kutty f3959cb5b9 zcu102- 2016.4 updates 2017-05-18 14:17:20 -04:00
Rejeesh Kutty 4f0accbbfa adrv9371x fix dacfifo name 2017-05-18 12:54:14 -04:00
Rejeesh Kutty d507cd0c9a quartus optimization for frequency 2017-05-18 11:34:29 -04:00
Rejeesh Kutty 80a3f45b9f alt_mul- qsys replacement 2017-05-18 10:38:48 -04:00
Rejeesh Kutty ff7dc41066 alt-jesd- constraints update 2017-05-18 09:55:24 -04:00
Rejeesh Kutty d10faabc3f a10soc- 16.1- hsp sdram reset 2017-05-17 16:30:37 -04:00
Rejeesh Kutty f8f7bdd6a6 a10soc- fix version check 2017-05-17 16:26:28 -04:00
Rejeesh Kutty 598bd7e226 resolving conflicts 2017-05-17 16:18:53 -04:00
Rejeesh Kutty 6649b23bc8 alt-mem-asym - replace mega function cores 2017-05-17 16:13:26 -04:00
Rejeesh Kutty 828c2406cb adi-ip-alt allow changing device family 2017-05-17 16:13:26 -04:00
Rejeesh Kutty bea72232a3 alt_mem_asym- qsys component 2017-05-17 16:13:26 -04:00
Istvan Csomortani fe140a054f license: Fix VHDL license header 2017-05-17 18:28:06 +03:00
AndreiGrozav 70e3dd00ff scripts: Update required tool versions 2017-05-17 16:45:20 +03:00
Lars-Peter Clausen bf44f357fe Fix VHDL files license header, second try
While VHDL uses -- for comments uris still use //.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-05-17 15:25:08 +02:00
Lars-Peter Clausen 5ee9480142 Fix VHDL files license header
VHDL uses '--' for comments rather than '//'.

Also remove left over old license headers.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-05-17 15:21:06 +02:00
AndreiGrozav 18bc5465df axi_usb_fx3: Add missing ports 2017-05-17 14:48:28 +03:00
Istvan Csomortani 9055774795 all: Update license for all hdl source files
All the hdl (verilog and vhdl) source files were updated. If a file did not
have any license, it was added into it. Files, which were generated by
a tool (like Matlab) or were took over from other source (like opencores.org),
were unchanged.

New license looks as follows:

Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.

Each core or library found in this collection may have its own licensing terms.
The user should keep this in in mind while exploring these cores.

Redistribution and use in source and binary forms,
with or without modification of this file, are permitted under the terms of either
 (at the option of the user):

  1. The GNU General Public License version 2 as published by the
     Free Software Foundation, which can be found in the top level directory, or at:
https://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html

OR

  2.  An ADI specific BSD license as noted in the top level directory, or on-line at:
https://github.com/analogdevicesinc/hdl/blob/dev/LICENSE
2017-05-17 11:52:08 +03:00
AndreiGrozav 857ad45d57 util_fir_int: Force 1/8 filter input data rate 2017-05-16 19:35:24 +03:00
AndreiGrozav 3f5d930cde axi_adc_decimate/cic_decim: Fix clk_enable warning
- fix clk_enable zero replication warning
2017-05-16 19:35:24 +03:00
AndreiGrozav fd7db4fcf3 util_tdd_sync: add missing ports 2017-05-16 19:35:24 +03:00
AndreiGrozav cf3737122b Remove duplicare wire declaration
-Introduced by updating to verilog-2001
2017-05-16 19:35:24 +03:00
AndreiGrozav 41e25e7c96 Add missing ad_serdes_out interface ports 2017-05-16 19:35:24 +03:00
Rejeesh Kutty c4b4bdc415 daq2/a10gx- constraints remove 16.0 2017-05-16 10:09:42 -04:00
Adrian Costina 0c5dabe358 axi_ad9963: Update constraints as adc_common and dac_common paths have been renamed 2017-05-15 18:59:09 +03:00
Adrian Costina ce4f9bf906 up_dac_common: rename internal signals 2017-05-15 18:58:26 +03:00
Rejeesh Kutty cfcb269d38 a10gx- change ddr to 1G 2017-05-15 09:32:36 -04:00
Rejeesh Kutty 63b701ccab altera- add version check 2017-05-12 15:13:29 -04:00
Rejeesh Kutty ebeebdddf0 altera- infer latest versions 2017-05-12 13:40:14 -04:00
Rejeesh Kutty c728299e71 altera- default to latest version 2017-05-12 13:25:17 -04:00
Rejeesh Kutty ecfa15bfce version check- change to critical warning 2017-05-12 09:51:48 -04:00
AndreiGrozav e4ae391237 axi adc cores: Add missing ports to up_adc_common instance 2017-05-12 13:39:05 +03:00
AndreiGrozav 0e1e507541 axi dac cores: Add missing ports to up_dac_common instance 2017-05-12 13:37:34 +03:00
Rejeesh Kutty d93a6d062e fmcadc5-sync: added a convenience timer 2017-05-11 12:39:39 -04:00
Istvan Csomortani 8e7b577c94 axi_ad5766: Add missing ports to up_dac_common instance 2017-05-11 17:25:31 +03:00
Istvan Csomortani 6e5d965211 axi_ad5766: sdo_mem size is 3 2017-05-11 17:25:31 +03:00
Istvan Csomortani 7968ca64a6 axi_ad5766: Delete redundant parameters 2017-05-11 17:25:31 +03:00
Istvan Csomortani e327166cf2 axi_generic_adc: Update port names for up_adc_common instance 2017-05-11 11:00:24 +03:00
Rejeesh Kutty 039ae9ae92 fmcadc5- syntax/port name fixes 2017-05-10 16:30:15 -04:00
Rejeesh Kutty fea6eb68be up_adc_common- port name changes 2017-05-10 14:45:17 -04:00
Rejeesh Kutty 6a0a2e4661 hdlmake.pl updates 2017-05-10 14:35:06 -04:00
Rejeesh Kutty 74c44cf830 axi_fmcadc5- remove pack-driver is too late 2017-05-10 14:33:56 -04:00
Rejeesh Kutty c2dd991736 axi_fmcadc5- sign-extend and interleave (core is too late) 2017-05-10 14:33:56 -04:00
Rejeesh Kutty 78435ebbb7 ad9625- add an option to control cs monitoring 2017-05-10 14:33:56 -04:00
Rejeesh Kutty d374f5b091 library/up_adc_common- add sref sync option 2017-05-10 14:33:56 -04:00
Rejeesh Kutty 61bbfb2c82 library/axi_fmcadc5_sync- remove dependecy on adc-core (driver shows up late) 2017-05-10 14:33:56 -04:00
AndreiGrozav c44de7021a axi_ad9739a: Fix DDS set frequency
- DDS out frequency was 4 times greater than the desired frequency
2017-05-10 17:39:00 +03:00
Istvan Csomortani 5fe008d887 axi_ad9371: Update dac_clk_ratio to 2
DAC sampling frequency is two times of the JESD204
core clock.
2017-05-10 11:12:45 +03:00
Rejeesh Kutty 0e5a24ee7c axi_fmcadc5_sync- raw inputs & constraint fixes 2017-05-08 10:30:51 -04:00