* SPI Engine: Add registers for Offload memory and FIFO sizes
Adds registers at dword 0x04 and 0x05, respectively allowing software
to get the sizes of the Offload Module memories (command and sdo) or
the sizes of the FIFOs on the AXI regmap.
Signed-off-by: Laez Barbosa <laez.barbosa@analog.com>
Use tcl script instead of static xmls for the interface.
Easier to maintain and are not gitignored.
Rename spi_master to spi_engine because every interface should be
prefixed by the IP name; in this case, spi_engine.
Also, remove interface/*.sv files on make clean and git ignore them.
Signed-off-by: Jorge Marques <jorge.marques@analog.com>
The extensions have been moved to docs tools.
The source code is available at
https://github.com/analogdevicesinc/doctools
And is installed as before:
(cd docs ; pip install -r requirements.txt --upgrade)
Since the package is listed on the requirements.txt file.
Also, add index for library and projects
Signed-off-by: Jorge Marques <jorge.marques@analog.com>
Set validation ranges for DATA_WIDTH and NUM_OF_CS for the expected
min/max values in the verilog source code.
Also, fix swapped description for CPHA in the documentation.
Signed-off-by: Carlos Oliveira <caosjr8@gmail.com>
Replaces Symbolator with custom component diagram generator for more
reliable diagrams.
It uses the IP-XACT file, if it is not found, a placeholder is added
instead.
Signed-off-by: Jorge Marques <jorge.marques@analog.com>
Import aiohttp and asyncio only when needed.
Better warning for unknown signals, params.
Use pattern matching in regmap parsing.
Fixup bundle count.
Add lists clarification to guidelines.
Enforce #1229 rules.
Clean-up Makefile.
Use non-breaking hyphen.
Signed-off-by: Jorge Marques <jorge.marques@analog.com>
* SPI Engine: Add execution delay documentation
Add documentation for the different delays on the command path and
data path, including communication between submodules and instruction
execution overhead.
Signed-off-by: Laez Barbosa <laez.barbosa@analog.com>
* docs: Improve consistency
The following rules have been implemented:
1. Tables/lists should contain only the carriers that we support for
that reference design.
2. Hexadecimal addresses should be written in caps and separated
by an underscore (eg. 0x9C4A_0000).
3. Block diagrams should contain subtitles only if there are at
least two different diagrams.
4. The GPIOs should be listed in descending order and should have
the number of bits specified next to their name.
5. All the source code links references should contain the project
name.
6. The infrastructure documentation, if exists, should be listed
after the IP list.
Recommend storing images like any other artifact: in a hierarchical
manner, without "images" subfolders.
This is intended to avoid dangling artifacts when projects are moved,
renamed, or deleted.
Recommend overwriting the page title with a shorter title in the
toctree, so the navigation bar doesn't overflow or get too cluttered.
Add acostina to CODEOWNERS
Signed-off-by: Jorge Marques <jorge.marques@analog.com>
Drop part role, use generic adi instead for root adi domain links.
For future reference, the snipped used was:
find ./docs/projects -type f -exec sed -i 's/:part:/:adi:/g' {} \;
Drop Containerfile.
Add option to validate links status (e.g. 200, 404), intended mostly for CI
use to check if a page has disappeared from the internet.
Validate links uses coroutines to launch multiple tasks concurrently,
but do it in bundles to avoid being rate limited.
Fixup regmap styling.
Add imoldovan, jmarques, spop, lbarbosa as docs codeowners.
Remove branch field for links to the hdl repo.
Change git role to display full path.
Fixup ZedBoard link label, remove IP List, add SYSID_ROM dokuwiki link
in ad716_sdz project.
Signed-off-by: Jorge Marques <jorge.marques@analog.com>
Fixed wrong behaviour on chip select instruction:
- previously, a sleep time happened before the chip select change
- the intended behaviour was for another sleep time, of equal amount, to happen after the chip select change as well
- additionally, the counter logic implementation was creating an additional factor of 2 on the sleep time
All of the above points were fixed. The changes introduced also fix another issue where the sleep instruction was likewise happening with a duration larger than intended by a factor of 2
Signed-off-by: Laez Barbosa <laez.barbosa@analog.com>
* Created the template for the HDL project documentation
* Added the More information and Support pages as two separate files
which will be embedded in the project documentations
Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
* Created the first level of pages for the User guide, from Analog Wiki:
* Architecture
* Build HDL
* Customize HDL
* Docs guidelines (edited)
* Git repository
* HDL coding guideline (edited)
* Introduction
* IP cores
* Porting projects (edited)
* Releases
* Third party
* Moved hdl_coding_guideline under user_guide and changed extension to rst
* Deleted hdl_pr_process.md
* docs_guideline: Add reference to project doc template
* porting_project:
Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
* Remove sphinxcontrib.mermaid extension
* Added red and green role
* Fixed the :part: role link because analog.com doesn't know to
redirect to proper part webpage if it's under /products
Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
Update docs instructions in the README.md to recommend building the libraries before generating the documentation.
Fix misspellings in the SPI Engines.
Use hashlib to gen the reproducible ids, so these elements won't be committed at every build in the gh-pages branch.
Get username from environment variable, to use in the symbolator local installation path, dismissing user interaction for this.
Use modelParameter to extract the type from ip-xact parameters without the format field, and improve formatting.
Signed-off-by: Jorge Marques <jorge.marques@analog.com>
-Updated description of some fields of these registers: REG_CHAN_CNTRL_1,
REG_CHAN_CNTRL_2, REG_CHAN_CNTRL_3, REG_CHAN_CNTRL_4, REG_USR_CNTRL_4,
and REG_USR_CNTRL_5
-Added two new registers, both with their own fields and description:
REG_CHAN_CNTRL_9 and REG_CHAN_CNTRL_10
Signed-off-by: Cristian Mihai Popa <cristianmihai.popa@analog.com>
Signals/buses declared in the docs that does not exist in the
components.xml files will raise a warning.
Signed-off-by: Jorge Marques <jorge.marques@analog.com>
Add documentation info to the README.md
At adi_hdl_parser.py, filter "_signal_clock" and "_signal_reset"
pseudo buses from component.xml files, append them as description
in the ports table, in the format
"{Bus} [...] is synchronous to this {domain}".
Also, adds collapsible directive
Signed-off-by: Jorge Marques <jorge.marques@analog.com>
Moves guidelines to user_guide as docs_guidelines.
Includes Porting HDL project user guide.
Replaces the Excel spreadsheet with raw space divided files.
Includes the 6 pinned at the org.
Contributors shall expand the list as needed.
Signed-off-by: Jorge Marques <jorge.marques@analog.com>
Stanca Pop
Sergiu Arpadi
LBFFilho
Jorge Marques
PIoandan
Iulia Moldovan
Alin-Tudor Sferle
laurent-19
caosjr
Jorge Marques
cristianmihaipopa
Ionut Podgoreanu
StancaPop
Ramon Cristopher Calam
PopPaul2021
Cristian Mihai Popa