2b5136db98
scripts/project_intel.mk: Update CLEAN targets
2020-09-09 14:15:37 +03:00
f9c4283f45
stratix10soc: Initial commit of base design
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Note: Currently we have a engineering sample version 2 board.
2020-09-09 14:15:37 +03:00
eb2f211d30
scripts/intel: Add message severity definition file
2020-08-25 14:46:52 +03:00
fa0b39fa20
adi_project_intel: Update QSYS generation
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In Quartus Prime in place of the set_domain_assignment command, the
set_interconnect_requirement command is used.
2020-08-17 12:02:49 +03:00
f3b69c15c9
scripts/intel: Update version check
2020-08-12 10:33:29 +03:00
218f45a0df
scripts/intel: Set supported Quartus version to 19.3
2020-08-12 10:33:29 +03:00
5ba3448987
scripts/project-intel: Update CLEAN target
2020-08-11 10:14:18 +03:00
8fd1ad64d6
quartus: Increase tool version to 19.2
2020-08-11 10:14:18 +03:00
f3142a6a7a
adi_project_intel: set_interconnect_requirment command is deprecated
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Use set_domain_assignment to set up the maximum pipeline stages for the
main interconnect.
2020-08-11 10:14:18 +03:00
967a138d0f
adi_project_intel: Add support for Quartus Pro
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By defualt the supported tool chain is Quartus PRO. If you want to
build the project with Quartus Standard, you need to define an environment
variable called QUARTUS_PRO_ISUSED with the value 0. (e.g. export
QUARTUS_PRO_ISUSED=0 )
Note: Not all projects going to build on Quartus Standard, you should
fix the errors if there is any.
2020-08-11 10:14:18 +03:00
054193e083
adi_project_intel: Delete all MESSAGE_DISABLE assignment
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These kind of assignments should be placed into file like
~/projects/scripts/adi_xilinx_msg.tcl
2020-08-11 10:14:18 +03:00
4ca1311d57
quartus_pro: Global assignment ENABLE_ADVANCED_IO_TIMING is not supported
2020-08-11 10:14:18 +03:00
9c8190f709
adi_project_xilinx.tcl: discover all timing failures
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Look for an overall indicator of timing failure.
Create critical warning if timing is failed.
2020-05-26 14:47:38 +03:00
db6af63583
scripts/adi_env.tcl: print in logs system variables are used
2020-05-20 19:07:23 +03:00
6535e5b2ba
scripts/xilinx: Version mismatch is upgraded to ERROR
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There is a major compatibility issue between 2019.1 and 2019.2.
The file system_top.hdf got a different file extention. This will
cause a compilation failer in the end of the build. To save time
and fail earlier, upgrade the version mismatch message to ERROR.
If user still wants to build a branch with different tool version
the variable ADI_IGNORE_VERSION_CHECK should be set to 1.
2020-05-15 12:16:35 +03:00
1f7671cb36
scripts/adi_env.tcl: helper function for environment variables
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Ease the access of the environment variables.
2020-03-10 18:19:03 +02:00
3192807f22
adi_project_xilinx: Fixed variable name
2020-02-14 11:22:46 +02:00
c5e03eb196
adi_project_xilinx: Added power analysis procedure
2020-02-14 11:22:46 +02:00
78a1e54a33
adi_project_xilinx.tcl: Generate resource utilization for IPs
2020-02-13 11:33:02 +02:00
135538b521
adi_project: Fixed kcu105 board file selection
2020-01-16 17:16:58 +02:00
e773b22087
adi_project: Updated board files version selection
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vivado will automatically select the latest version for a given board
2020-01-14 17:16:01 +02:00
d86fbb2a08
adi_board: fixed ddr memory mapping for microblaze projects
2020-01-13 12:25:23 +02:00
34ea5efdff
adi_project_xilinx: Use the latest board files
2020-01-13 12:25:23 +02:00
adfeb435a4
scripts: Update Vivado version to 2019.1
2020-01-13 12:25:23 +02:00
82021edffe
adi_board.tcl:ad_xcvrcon: do not reorder common control
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When channels are not swapped in groups of four but are completely out of order
the common control channel can't be reordered based on the index of the
channel.
2019-11-30 12:29:32 +02:00
8c39cf8560
scripts: adi_board.tcl: Update the axi_adxcvr to util_adxcvr connections
2019-11-26 12:57:53 +02:00
40d839df5f
coraz7s: Initial commit
2019-11-15 14:35:00 +02:00
fd4d32c408
projects/scripts/*xilinx*: Generate report utilization extra files
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Add commands to generate one extra file with resource utilization, in CSV format.
New commands executes only if ADI_GENERATE_UTILIZATION env variable is set.
2019-10-18 13:42:34 +03:00
af94487f57
adi_project_intel: Enable HPS internal timing
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It's recommended to use this global assignment so the tool can make a
more in-depth timing analysis.
2019-10-02 15:32:17 +03:00
75d263afc5
adi_project_xilinx: Add constraint files to constr_1 file set
2019-09-27 18:21:25 +03:00
b174333fa2
project-xilinx.mk: Clean generated file by sysid
2019-09-27 13:16:19 +03:00
442b38033a
sys_id: added catch to git status check
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made error checking more general
2019-09-26 16:26:02 +03:00
5e08e2d548
project-xilinx.mk: Fix build condition
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"prepare_incremental_compile" is defined as a phony target, but is also a
prerequisite of a real target. This will lead to a complete project build
every time make is called.
To fix the issue the functionality of prepare_incremental_compile target
was included in the generic project build target.
2019-09-12 13:23:09 +03:00
36a1767329
Add generic fir filters processes for RF projects
2019-08-20 16:24:47 +03:00
4fe5f007cb
system_id: added axi_sysid ip core and tcl
2019-08-06 16:53:11 +03:00
14a4acfd0e
projects/scripts: Fix a typo in adi_env.tcl
2019-07-25 17:58:36 +03:00
fa610d36c6
ad_ghdl_dir: Fix global variable name
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In #PR318 the global variable $ad_phdl_dir name were changed to
$ad_ghdl_dir.
2019-07-23 10:29:37 +01:00
6a721c0bf0
adi_env: Update system level environment variable definition
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Our internal repository was changed from phdl to ghdl. Update the
adi_env.tcl scripts and other scripts, which depends on the $ad_ghdl_dir
variable. This way the tools will see all the internal IPs too.
2019-07-22 11:00:45 +03:00
e1d9a36ae0
scripts/adi_project_intel: Rename ALT_NIOS_MMU_ENABLED to NIOS_MMU_ENABLED
2019-06-29 06:53:51 +03:00
363494ab9c
library/scripts: Rename adi_ip.tcl to adi_ip_xilinx.tcl
2019-06-29 06:53:51 +03:00
6e6f1347d7
project/scripts: Rename adi_project_alt.tcl to adi_project_intel.tcl
2019-06-29 06:53:51 +03:00
a589753d92
project/scripts: Rename adi_project.tcl to adi_project_xilinx.tcl
2019-06-29 06:53:51 +03:00
43725429ac
adi_project: Rename the process adi_project_xilinx to adi_project
2019-06-29 06:53:51 +03:00
ec67a381e4
adi_project: Rename the process adi_project_altera to adi_project
2019-06-29 06:53:51 +03:00
79b6ba29ce
all: Rename altera to intel
2019-06-29 06:53:51 +03:00
993497438b
adi_project:adi_project_run: Check if $num_reg exist
2019-06-11 18:13:06 +03:00
896ea4925d
adi_board: Fix ad_mem_hpx_interconnect proc
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Make the lsearch command more robust.
2019-06-11 18:13:06 +03:00
20c714eccf
common: Define three global clock nets
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For all the Xilinx base design, define three global clock nets, which
are saved in the following three global variable: $sys_cpu_clk, $sys_dma_clk
and $sys_iodelay_clk.
These clock nets are connected to different clock sources depending of
the FPGA architecture used on the carrier. In general the following
frequencies are used:
- sys_cpu_clk - 100MHz
- sys_dma_clk - 200MHz or 250Mhz
- sys_iodelay_clk - 200MHz or 500Mhz
2019-06-11 18:13:06 +03:00
a7e3fcf26a
adi_project_alt.tcl: Add comments to all proc
2019-05-31 10:32:40 +03:00
41bc947ac1
adi_project.tcl: Add comments to all proc
2019-05-31 10:32:40 +03:00
Istvan Csomortani
Laszlo Nagy
Sergiu Arpadi
sraus
Adrian Costina
Stanca Pop
AndreiGrozav
István Csomortáni