Import aiohttp and asyncio only when needed.
Better warning for unknown signals, params.
Use pattern matching in regmap parsing.
Fixup bundle count.
Add lists clarification to guidelines.
Enforce #1229 rules.
Clean-up Makefile.
Use non-breaking hyphen.
Signed-off-by: Jorge Marques <jorge.marques@analog.com>
Drop part role, use generic adi instead for root adi domain links.
For future reference, the snipped used was:
find ./docs/projects -type f -exec sed -i 's/:part:/:adi:/g' {} \;
Drop Containerfile.
Add option to validate links status (e.g. 200, 404), intended mostly for CI
use to check if a page has disappeared from the internet.
Validate links uses coroutines to launch multiple tasks concurrently,
but do it in bundles to avoid being rate limited.
Fixup regmap styling.
Add imoldovan, jmarques, spop, lbarbosa as docs codeowners.
Remove branch field for links to the hdl repo.
Change git role to display full path.
Fixup ZedBoard link label, remove IP List, add SYSID_ROM dokuwiki link
in ad716_sdz project.
Signed-off-by: Jorge Marques <jorge.marques@analog.com>
Update docs instructions in the README.md to recommend building the libraries before generating the documentation.
Fix misspellings in the SPI Engines.
Use hashlib to gen the reproducible ids, so these elements won't be committed at every build in the gh-pages branch.
Get username from environment variable, to use in the symbolator local installation path, dismissing user interaction for this.
Use modelParameter to extract the type from ip-xact parameters without the format field, and improve formatting.
Signed-off-by: Jorge Marques <jorge.marques@analog.com>
Signals/buses declared in the docs that does not exist in the
components.xml files will raise a warning.
Signed-off-by: Jorge Marques <jorge.marques@analog.com>
Add documentation info to the README.md
At adi_hdl_parser.py, filter "_signal_clock" and "_signal_reset"
pseudo buses from component.xml files, append them as description
in the ports table, in the format
"{Bus} [...] is synchronous to this {domain}".
Also, adds collapsible directive
Signed-off-by: Jorge Marques <jorge.marques@analog.com>
Automate table generation for register maps.
Based on tfcollins' vger python scripts.
There are docs/adi_regmap_*.txt with more than one regmap per file,
so the logic changed to allow that.
Using title tool as the unique identifier now.
It has a global option to set the default state (hidden or visible)
for the collpasible tables.
Also remove CSVs.
Signed-off-by: Jorge Marques <jorge.marques@analog.com>
Uses Vivado generated components.xml files.
If the file is not found/generated, there is a fallback method.
Also, define bibliography per project, not globally.
Signed-off-by: Jorge Marques <jorge.marques@analog.com>
The parameters directive allows to almost automatically generate the
parameters table.
It allows to add rich descriptions to the parameters, such as references,
while checking if they exist in the *_hw.tcl file a obtaining the types
and default values.
However, it cannot obtain parameters generated from a foreach loop yet,
making it incompatible with the axi_dmac_hw.tcl file for example.
This commit also joins the other extensions into a single adi_links
extension.
Signed-off-by: Jorge Marques <jorge.marques@analog.com>
Jorge Marques
Jorge Marques