Import aiohttp and asyncio only when needed.
Better warning for unknown signals, params.
Use pattern matching in regmap parsing.
Fixup bundle count.
Add lists clarification to guidelines.
Enforce #1229 rules.
Clean-up Makefile.
Use non-breaking hyphen.
Signed-off-by: Jorge Marques <jorge.marques@analog.com>
* docs: Improve consistency
The following rules have been implemented:
1. Tables/lists should contain only the carriers that we support for
that reference design.
2. Hexadecimal addresses should be written in caps and separated
by an underscore (eg. 0x9C4A_0000).
3. Block diagrams should contain subtitles only if there are at
least two different diagrams.
4. The GPIOs should be listed in descending order and should have
the number of bits specified next to their name.
5. All the source code links references should contain the project
name.
6. The infrastructure documentation, if exists, should be listed
after the IP list.
Recommend storing images like any other artifact: in a hierarchical
manner, without "images" subfolders.
This is intended to avoid dangling artifacts when projects are moved,
renamed, or deleted.
Recommend overwriting the page title with a shorter title in the
toctree, so the navigation bar doesn't overflow or get too cluttered.
Add acostina to CODEOWNERS
Signed-off-by: Jorge Marques <jorge.marques@analog.com>
Drop part role, use generic adi instead for root adi domain links.
For future reference, the snipped used was:
find ./docs/projects -type f -exec sed -i 's/:part:/:adi:/g' {} \;
Drop Containerfile.
Add option to validate links status (e.g. 200, 404), intended mostly for CI
use to check if a page has disappeared from the internet.
Validate links uses coroutines to launch multiple tasks concurrently,
but do it in bundles to avoid being rate limited.
Fixup regmap styling.
Add imoldovan, jmarques, spop, lbarbosa as docs codeowners.
Remove branch field for links to the hdl repo.
Change git role to display full path.
Fixup ZedBoard link label, remove IP List, add SYSID_ROM dokuwiki link
in ad716_sdz project.
Signed-off-by: Jorge Marques <jorge.marques@analog.com>
* Created the template for the HDL project documentation
* Added the More information and Support pages as two separate files
which will be embedded in the project documentations
Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
Automate table generation for register maps.
Based on tfcollins' vger python scripts.
There are docs/adi_regmap_*.txt with more than one regmap per file,
so the logic changed to allow that.
Using title tool as the unique identifier now.
It has a global option to set the default state (hidden or visible)
for the collpasible tables.
Also remove CSVs.
Signed-off-by: Jorge Marques <jorge.marques@analog.com>
Jorge Marques
StancaPop
Stanca Pop
Jorge Marques
Iulia Moldovan