5 Commits (9f8a94df69b73a510ff2168ba7ccd6e93f2a2660)

Author	SHA1	Message	Date
Rejeesh Kutty	ebeebdddf0	altera- infer latest versions	2017-05-12 13:40:14 -04:00
Rejeesh Kutty	b3ce821311	change pl ddr clock to 1G	2017-05-01 09:35:10 -04:00
Istvan Csomortani	6ed721ee66	adrv9371/a10soc: Integrate the avl_dacfifo into project	2017-04-21 13:27:35 +03:00
Rejeesh Kutty	3fa9a30f0e	a10soc/plddr4- lower mem clk to meet timing	2017-03-06 14:12:25 -05:00
Rejeesh Kutty	aad41039bd	a10soc- plddr4 settings	2017-02-28 13:36:28 -05:00