Commit Graph

16 Commits (9fa705c4881d0992436d8fa9ee9a491f6836e444)

Author SHA1 Message Date
Istvan Csomortani 1fcdeac054 fmcjesdadc1/common: The new GT module does not have integrated monitor/debug ports 2015-06-09 11:50:55 +03:00
Rejeesh Kutty 71b5004b25 projects- drp moved to up-clock domain 2015-06-01 14:57:59 -04:00
Adrian Costina e332fa01c8 ad6676evb, daq2, fmcadc2, fmcjesdadc1, usdrx1: Updated jesd reset connection 2015-04-30 12:11:46 +03:00
Adrian Costina c7e4ba5083 fmcjesdadc1: Updated KC705 to the latest flow 2015-03-30 18:07:47 +03:00
Adrian Costina ccf0542218 fmcjesdadc1: Connected constant 0 to unconnected inputs 2015-03-26 12:08:14 +02:00
Adrian Costina d418c9f9b1 fmcjesdadc1: Updated project to new flow. Updated ZC706 design 2015-03-24 10:38:14 +02:00
Michael Hennerich 138e789fb6 projects/fmcjesdadc1/common/fmcjesdadc1_bd.tcl: Fix interrupts
sys_concat_intc: don't reset NUM_PORTS to 6

Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
2014-12-09 17:38:16 +01:00
Istvan Csomortani b0f571ce0c fmcjesdadc1: Fix parameter lane number for GT core 2014-11-21 19:17:29 +02:00
Istvan Csomortani 57137df018 fmcjesdadc1_zc706: Interrupt update 2014-11-03 13:02:09 +02:00
Istvan Csomortani 17675863e0 all_projects: Fix the interrupt connections to preserve IRQ layout 2014-10-22 11:48:08 +03:00
Istvan Csomortani 02802644bf fmcjesdadc1: Fix a few warning and issue with ILA
+ GPIO width is 15
+ Fix ILA core
2014-10-15 15:37:05 +03:00
Istvan Csomortani 6f77af4aff fmcjesdadc1: Upgrade project to 2014.2 2014-10-09 18:55:27 +03:00
Istvan Csomortani 2ce7695bf7 fmcjesdadc1: Initial commit of VC707 version 2014-09-01 18:47:01 +03:00
Istvan Csomortani 9a80fec4e4 fmcjesdadc1: Delete trailing whitespaces 2014-09-01 18:45:20 +03:00
Rejeesh Kutty 5f21f54463 fmcjesdadc1: zc706 version 2014-08-25 14:28:57 -04:00
Rejeesh Kutty 76ffb939e5 zc706: ad9625 copy 2014-08-22 11:24:24 -04:00