Commit Graph

30 Commits (9fa705c4881d0992436d8fa9ee9a491f6836e444)

Author SHA1 Message Date
Rejeesh Kutty f81d22a17a altera- common timing check 2015-06-04 10:56:32 -04:00
Adrian Costina c19749361d Makefiles: Updated makefiles to have as a result the programming file instead of the project file.
Also fixed altera projects dependencies
2015-05-18 17:22:46 +03:00
Adrian Costina 293ec6a319 fmcomms2: c5soc project updated to 14.1 2015-05-08 17:44:16 +03:00
Adrian Costina dc2b37bd0c Makefile: Added top level Makefile. Modified behavior of clean and clean-all
Clean ran for a project will clean only the project files.
Clean-all ran for a project will clean also the library files on which the project depends.
The clean commands will only remove specific files and directories.

The top Makefile allows several options(per suggestion from jameyhicks):
make fmcomms1.zed will run "make all" in projects/fmcomms1/zed/
make clean will run "make clean" for all the projects
make clean-all will run "make clean" for all the projects and libraries
make lib will run "make all" for the library files
2015-04-17 17:22:38 +03:00
Adrian Costina 374f82e7de makefiles: The clean command for library won't remove the xml files, except for component.xml.
Updated also the dmac dependencies
2015-04-16 11:53:27 +03:00
Adrian Costina 780455d68c Makefile: Updated makefiles. Added makefiles for altera 2015-04-09 17:57:06 +03:00
Rejeesh Kutty 5f8e9a74ea makefile: updated 2015-04-07 16:32:01 -04:00
Adrian Costina f79a152958 Makefiles: updated all makefiles adding clean functionality 2015-04-03 11:57:54 +03:00
Rejeesh Kutty 61bdb437b1 makefile: added 2015-04-01 16:29:33 -04:00
Adrian Costina 86ad9213e0 fmcomms2: Update c5soc system_timing script 2014-12-10 17:54:11 +02:00
Lars-Peter Clausen d8651cdd2e fmcomms2: c5soc: Set dac_util_unpack number of channels to 4
We only do have 4 channels in this design. Reducing the number of supported
channels for the dac_util_unpack core to 4 from 8 lowers the DMA alignment
requirement from 128bit to 64bit.  We need this since applications only
expect a DMA alignment requirement of 64bit.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-09-12 16:15:12 +02:00
Lars-Peter Clausen ecc498313c fmcomms2: c5soc: Connect ADC, DAC and VGA DMA to different bridge interconnects
We have enough bridge interconnect to give each DMA its own, so use them.
This makes sure that they do not interfere with each others transfers to
much. The SDRAM controller side of the FPGA2SDRAM bridges FIFO runs at a
much faster frequency then what we are able to use in the fabric. So its
better to do the arbitration on that side of the bus to make sure that we
can utilize the buses in the FPGA fabric to the maximum for each DMA core.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-09-12 16:14:07 +02:00
Adrian Costina 61f21a17b3 fmcomms2:c5soc project upgraded with util_dac_unpack 2014-09-11 15:13:09 -04:00
Lars-Peter Clausen 4c1c50788e fmcomms5: c5soc: Fix typo
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-09-11 17:15:10 +02:00
Lars-Peter Clausen c7989925c5 fmcomms2: c5soc: Add false path between 50MHz and VGA PLL clock
Otherwise we get timing errors for the reset signal that is generated in the
50MHz clock domain, but used in the VGA PLL clock domain.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-09-09 15:05:06 +02:00
Lars-Peter Clausen 328205c31d fmcomms2: c5soc: Set DMA transfer length to 24 bits
14 bits is a bit to low and we use 24 bits everywhere else as well.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-09-09 15:05:06 +02:00
Lars-Peter Clausen 50faf0c53a Remove executable flags from non-exectuable files 2014-09-09 15:05:06 +02:00
dbogdan 5a42c10233 projects/fmcomms2/c5soc: Added video output. HPS SPI was replaced by 3 Wire SPI. 2014-08-27 21:46:23 +03:00
Rejeesh Kutty 280260e54c c5soc: dmac separated slave and master id widths 2014-08-22 09:08:54 -04:00
Rejeesh Kutty 7bee85423d c5soc: removed stp/cdf files 2014-07-24 20:53:08 -04:00
Rejeesh Kutty 59759a8ab3 c5soc: working hdl version 2014-07-24 20:51:41 -04:00
Rejeesh Kutty c0e31aa6c2 daq2: latest hardware 2014-07-21 09:06:57 -04:00
Rejeesh Kutty e3320c43cb fmcomms2/c5soc: programmer file 2014-07-21 09:06:55 -04:00
Rejeesh Kutty 9b9e0c6a56 fmcomms2/c5soc: signal tap 2014-07-21 09:06:54 -04:00
Rejeesh Kutty 2955b9db78 fifo2s: flush if no request, c5soc: 14.0 2014-07-15 16:25:33 -04:00
Adrian Costina 39ac29bb01 AD9361: Altera, modified address width so that all registers are accessible
Modified qsys project with the new address span
2014-07-08 10:41:51 +03:00
dbogdan 10c21a343a fmcomms2/c5soc: Fixed the spim0_ss_in_n value. 2014-07-08 10:07:31 +03:00
dbogdan c53b257ab1 fmcomms2/c5soc: Fixed the MOSI and MISO pin assignments. 2014-07-07 22:28:25 +03:00
Rejeesh Kutty a388ccab0a fmcomms2/c5soc: initial checkin 2014-07-02 14:56:00 -04:00
Rejeesh Kutty 9a08189b93 c5soc: initial a5soc copy 2014-07-01 13:09:38 -04:00