zcy
/
pluto_hdl_adi
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity
3,461 Commits
1 Branch
0 Tags
23 MiB
Commit Graph

5 Commits (9feeb726310af7fe6c0ba2bec3dd24d2115ae41c)

Author SHA1 Message Date
Istvan Csomortani 343d0472d4 fmcadc2: Move GT setting to common/system_bd.tcl 2017-02-16 14:56:25 +02:00
Istvan Csomortani 07184b31d2 fmcadc2: Define default clock selection for Xilinx GTs 2017-02-16 12:35:24 +02:00
Rejeesh Kutty ce1fed1ce6 dmafifo- adc/dac split 2016-08-16 12:54:39 -04:00
Istvan Csomortani bb185296d7 fmcadc2_vc707: Increase the BRAM FIFO size to its maximum: it can store 1M samples. 
The 2^18 dma address width with a 64 dma data width will result a FIFO, what will be implemented by 512 RAMB36 cells.
This is a the maximum BRAM FIFO depth in case of the VC707.
 2015-04-23 18:00:00 +03:00
Rejeesh Kutty 19e4950b72 renamed to match official names 2014-12-08 10:44:15 -05:00