Commit 5db7574 switched ad_cpu_interconnect from SmartConnect to
AXI Interconnect for Zynq-7000 family SoC. This commit does the
same for ad_mem_hpx_interconnect.
Signed-off-by: Alexander Vickberg <wickbergster@gmail.com>
Signed-off-by: Jorge Marques <jorge.marques@analog.com>
I changed the comments from system_constr.xdc file.
Added pulsar_adc_pmdz_pmod.txt.
Tests were done on the eval-ad7689-ebz and eval-ad7984-pmdz boards.
Signed-off-by: Ioan-daniel Pop <Pop.Ioan-daniel@analog.com>
* Update cn0363 spi engine
I replaced the SPI Engine connections in the cn0363_bd.tcl with the
spi_engine_create procedure found in the spi_engine.tcl script. Through
these changes, a more generic instantiation for the spi_engine can be
achieved. I updated the system_constr.xdc file and
created the cn0363_pmod.txt file.
Signed-off-by: Ioan-daniel Pop <Pop.Ioan-daniel@analog.com>
* Update ad469x spi engine
I replaced the SPI Engine connections in the ad469x_bd.tcl with the
spi_engine_create procedure found in the spi_engine.tcl script. Through
these changes, a more generic instantiation for the spi_engine can be
achieved. I also created the ad469x_fmc.txt file for generating the
system_constr.xdc file.
Signed-off-by: Ioan-daniel Pop <Pop.Ioan-daniel@analog.com>
* Update SPI Engine AD738x
I replaced the SPI Engine connections in the ad738x_bd.tcl with the
spi_engine_create procedure found in the spi_engine.tcl script. Through
these changes, a more generic instantiation for the spi_engine can be
achieved. I changed the ad738x_bd.tcl where it was added spi_engine_create
procedure, system_bd.tcl and system_top.v files.
I have update system_constr.xdc file and added ad738x_fmc.txt file.
Signed-off-by: Ioan-daniel Pop <Pop.Ioan-daniel@analog.com>
In this project it was created the ad5766_fmc.txt file for generating the system_constr.xdc file.
Also it was updated the system_constr.xdc and Readme.md files.
Signed-off-by: Ioan-daniel Pop <Pop.Ioan-daniel@analog.com>
I replaced the SPI Engine connections in the adaq7980_bd.tcl with the
spi_engine_create procedure found in the spi_engine.tcl script. Through
these changes, a more generic instantiation for the spi_engine can be
achieved. I configured the parameters for axi_pwm_gen and axi_clkgen according
to the results in the SPI_Engine_Timing_Computations Excel where I created a file
for adaq7980.
I created the adaq7980_fmc.txt file for generating the system_constr.xdc file.
I modified the system_bd.tcl, system_top.v, system_constr.xdc and Readme.md files.
Also I regenerated the Makefile.
This commit adds support for ADALM-PHASER, allowing the user to choose between the default PlutoSDR mode and Phaser mode
through a software controlled GPIO pin: phaser_enable.
The Generic TDD Engine was integrated to output a logic signal on the L10P pin, which connects to the input of the ADF4159,
when receiving an external synchronization signal on the L12N pin from the Raspberry Pi. Two additional TDD channels are used
to synchronize the TX/RX DMA transfer start:
- TDD CH1 is connected to the RX DMA, triggering the synchronization flag;
- TDD CH2 is connected to the TX unpacker's reset, backpressuring the TX DMA until deasserted.
Signed-off-by: Ionut Podgoreanu <ionut.podgoreanu@analog.com>
Reference design for AD4858 20-bit, low noise 8-channel, SAR ADC with
buffered differential, wide common range picoamp inputs.
The design supports:
- CMOS and LVDS interfaces(at build time)
- Runtime sampling changes
- Store captured samples in RAM, through DMA (available via software support)
Documentation at: https://wiki.analog.com/resources/eval/user-guides/ad4858_fmcz/ad4858_fmcz_hdl
The project controls the AD3552R digital-to-analog converter and transmits data written in the DDR memory to the QSPI interface of the DAC.
The reference clock is generated by an axi_clkgen IP and is configured to output a 133MHz signal.
If both channels are enabled and data streaming is DDR the sample rate is 16.65MSPS.
If just one channel is enabled and data streaming is DDR the sample rate is 33.3MSPS.
The VADJ voltage should be set to 1.8V.
Signed-off-by: PopPaul2021 <Paul.Pop@analog.com>
Change necessary to build intel projects with different system_top verilog files.
This was patterned to ae09b8a1bb/projects/scripts/project-xilinx.mk (L70)
Signed-off-by: Jem Geronimo <Johnerasmusmari.Geronimo@analog.com>
The generic project dependency list contains:
system_top*.v
system_bd.tcl
system_project.tcl
system_constr.xdc
This items will not be included in the auto generated makefiles. But
used as generic dependency.
This commit adds:
-wildcard check of system_constr*.xdc.
-wildcard check of system_constr*.tcl.
- Removes the reset_tx_pll_and_datapath_in reset
- Connects gtreset_in to make use of the master reset found inside
the Transceiver Bridge IP
- Connects the necessary signals for the master reset between the
Transceiver Wizard and Transceiver Bridge
ad9209/vck190/system_top: Connect versal transceiver reset
Signed-off-by: Bogdan Luncan <bogdan.luncan@analog.com>
The following CWs appeared (even in Vivado version 2021.2):
* CRITICAL WARNING: [BD 41-1356] Slave segment </sys_ps7/S_AXI_HP1/HP1_DDR_LOWOCM> is not assigned into address space </axi_rd_wr_combiner_logic/m_axi>. Please use Address Editor to either assign or exclude it.
* CRITICAL WARNING: [BD 41-1356] Slave segment </sys_ps7/S_AXI_HP2/HP2_DDR_LOWOCM> is not assigned into address space </axi_rd_wr_combiner_converter/m_axi>. Please use Address Editor to either assign or exclude it.
Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
Add a list with make commands with the proper parameters for each devicetree
availible at the moment.
Signed-off-by: LIacob106 <liviu.iacob@analog.com>
kylex
Iulia Moldovan
PIoandan
Bogdan Luncan
Ioan-daniel Pop
laurentiu_popa
Vilmos-Csaba Jozsa
Liviu.Iacob
Ionut Podgoreanu
AndreiGrozav
PopPaul2021
Jem Geronimo
Jem Geronimo
alin724
ladace
AndrDragomir
Filip Gherman