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3441 Commits (a09ee9d48104c4dcf637fc4ec0345172d30b466a)

Author SHA1 Message Date
Bogdan Luncan b21fb3a0e0 ad9081/common: Added ad9081_fmc.txt 
Signed-off-by: Bogdan Luncan <bogdan.luncan@analog.com>
 2023-05-10 12:59:58 +03:00
Bogdan Luncan 73af87a324 ad9081: Versal transceiver update 
- Remove 4 lane limitation
- Adds support for RX or TX only instantiation

Signed-off-by: Bogdan Luncan <bogdan.luncan@analog.com>
 2023-05-10 12:59:58 +03:00
Filip Gherman 5776511dd7 vcu118: Improve Microblaze Cache Performance for a better timing closure 2023-05-04 10:40:43 +03:00
Filip Gherman 2db55675f9 vcu128_system_bd.tcl: Additional microblaze interrupt for VCU128 2023-05-04 10:40:01 +03:00
Iulia Moldovan ea603b12a7 project-xilinx.mk: Update folders and files from make clean 
Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
 2023-04-28 17:02:13 +03:00
PIoandan 6a016c62db kc705 vc707: Increase linear flash capacity 2023-04-26 10:08:52 +03:00
Stanca Pop 1c8f210baf adi_project_xilinx.tcl: Add matlab env variables 
The ADI_EXTRACT_PORTS variable is used to extract all the ports and nets properties of the desired IPS for the TransceiverToolbox and HighSpeedConverterToolbox to be later used for generating the json files automatically.

The ADI_SKIP_SYNTHESIS variable is used to stop the building process before the synthesis when used with Matlab support as it is not necessary at this point.

The ADI_MATLAB variable is used to choose the correct paths when building the design when using the HWA workflow.
 2023-04-21 15:41:42 +03:00
ladace 4dee04f9c8
cn0561:de10nano: Updated Quartus version to 22.1Std (#1116) 2023-04-13 13:19:51 +03:00
ladace 34984e67c2
Quartus: Updated to Quartus Standard 22.1 (#1108) 2023-04-05 09:36:46 +03:00
sergiu arpadi cadb8e637d cn0561_de10nano: Initial commit 2023-03-30 14:55:59 +03:00
Sergiu Arpadi 4b704337d4 cn0540_de10nano: Update system_top, cleanup 2023-03-30 14:55:59 +03:00
alin724 7da9827782 ad7606x_fmc: Fix up_cpack2 module's SAMPLE_DATA_WIDTH parameter 2023-03-29 21:33:33 +03:00
laurent-19 2ae09c9808 Check guidelines. Remove redundancies 
* Removed empty/commented lines
 * Regenerated Makefiles
 * Removed redundancies adc channels data width
 * Set data width 32-bit: max resolution and CRC header

Signed-off-by: laurent-19 <laurentiu.popa@analog.com>
 2023-03-29 15:08:07 +03:00
laurent-19 1bef2bf304 projects/ad7134_fmc: Update bd SPIE hierarchy, spi trigger, ODR 
* Updated bd spi hierarchy, see library/spi_engine.tcl
 * Enabled ext_clk for PWM to use 96 MHz spi clk
 * Modified PWM channels used:
  - ch1: ODR - 850 ns period, 130 ns high time
	 ==> max fODR = 1.18 MHz
  - ch0: trigger - 850 ns period, 30 phase shift
         ==> 10 ns between falling ODR rising DCLK
 * Changed spi offload trigger signal:
  - replaced edge detect,sync_bits IPs with PWM trigger

Signed-off-by: laurent-19 <laurentiu.popa@analog.com>
 2023-03-29 15:08:07 +03:00
laurent-19 553774319a projects/cn0561: Update design: spi trigger, ODR, spi hierch 
* Enabled ext_clk for PWM to use 96 MHz spi clk
 * Modified PWM channels used:
  - ch1: ODR - 850 ns period, 130 ns high time
	 ==> max fODR = 1.18 MHz
  - ch0: trigger - 850 ns period, 30 phase shift
         ==> 10 ns between falling ODR rising DCLK
 * Changed spi offload trigger signal:
  - replaced edge detect,sync_bits IPs with PWM trigger
 * Updated bd SPIE hierarchy, see library/spi_engine.tcl

Signed-off-by: laurent-19 <laurentiu.popa@analog.com>
 2023-03-29 15:08:07 +03:00
Stanca Pop ee30c64923 projects/ad4134_fmc: Initial commit add support 
* Updated reference design: spi trigger, ODR parameters
  - enabled ext_clk for PWM to use 96 MHz spi clk
  - mofified PWM channels used:
  - ch1: ODR - 850 ns period, 130 ns high time
	 ==> max fODR = 1.18 MHz
  - ch0: trigger - 850 ns period, 30 phase shift
         ==> 10 ns between falling ODR rising DCLK
  - spi offload trigger signal: PWM trigger used
 * Moved mem_interconnect to hp1
 * Added dclkio GPIO
 * Updated bd SPIE hierarchy, see library/spi_engine.tcl

Signed-off-by: laurent-19 <laurentiu.popa@analog.com>
 2023-03-29 15:08:07 +03:00
Sergiu Arpadi 445cca61ef SPI Engine: Update spi_engine.tcl 
The SPI Engine cores were named directly inside the script and this
would mean that for multiple SPI Engine instances IPs with the same
name would appear. These updates will introduce the hierarchy name
into the name given to the cores and will therefore allow for
multiple instances of SPI Engine to be added to the same Xilinx
project.

Projects which use spi_engine.tcl will be updated to account for
these changes.
 2023-03-29 15:08:07 +03:00
Paul Pop 890569d53f projects/cn0579/de10nano: Fix Critical Warnings 
- Quartus version was updated
- the start_n output port was deteled from system_top.v
- the ""mixed_port_feed_through_mode" parameter of RAM can not have value "old"" warning was disabled
- update Makefile copyright year

Signed-off-by: Paul Pop <paul.pop@analog.com>
 2023-03-24 09:09:15 +02:00
Jem Geronimo 75adcb4e37
adi_project_intel.tcl: bugfix for ad_project_dir (#1101) 
bug:
  say "make LVDS_CMOS_N=0"
  - will set ad_project_dir as LVDSCMOSN0
  - will then set system_qip_file as LVDSCMOSN0/system_bd/synthesis/system_bd.qip
  - build error reveals system_bd can't be found
  - maybe due to setting ad_project_dir as a relative file path
fix:
  - set ad_project_dir as an absolute file path

Signed-off-by: Jem Geronimo <Johnerasmusmari.Geronimo@analog.com>
 2023-03-17 19:09:33 +08:00
Paul Pop b84d50bbb3 projects/cn0579: Initial commit for Coraz7s and DE10Nano 2023-03-16 16:20:44 +02:00
Iulia Moldovan 9977df074b vmk180_system_bd.tcl: Fix issue with PMC_I2C_PERIPHERAL 
* Issue appeared when updating to Vivado 2022.2

Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
 2023-03-09 09:53:41 +02:00
alin724 341ade7ae0 ad7606x: Fix system_top module's gpio instances and add missing adc_serpar,_refsel pins 2023-03-08 13:06:03 +02:00
PopPaul2021 2f7c8edef0 projects/*/a10gx: Support for A10GX carrier is discontinued. 2023-03-01 14:55:18 +02:00
Istvan-Zsolt Szekely 72461b2218 adi_board.tcl: Support multiple common channels connections between different TX adxcvr's and util_xcvr 
Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
 2023-02-09 17:08:18 +02:00
AndrDragomir a8a01aaaf4 projects/adrv9009zu11eg: Fix lane swap on tx1_c when used with fmcomms8 2023-02-03 11:00:33 +02:00
Iulia Moldovan db94628cc6 library & projects: Update Makefiles 
Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
 2023-01-27 11:54:05 +02:00
LIacob106 e932e6f4f8 projects/adrv9009zu11eg: JESD support for fmcomms8 
for configurations 4, 8 TX_L and 4 RX/ORX_L

Signed-off-by: LIacob106 <liviu.iacob@analog.com>
 2023-01-26 15:38:38 +02:00
LIacob106 261c0d1b90 projects/adrv9009zu11eg: JESD support for adrv2crr_fmc 
for configurations 2, 4 TX_L and 2 RX/ORX_L

Signed-off-by: LIacob106 <liviu.iacob@analog.com>
 2023-01-26 15:38:38 +02:00
LIacob106 9b8604b9a2 adrv9009/zc706: Add clkgen div to match the desired freq 2023-01-26 15:36:45 +02:00
LIacob106 911b8bbc99 projects/adrv9009: JESD support for 1, 2 TX_L and 1 RX/ORX_L 
Signed-off-by: LIacob106 <liviu.iacob@analog.com>
 2023-01-26 15:36:45 +02:00
LIacob106 10a87f34d3 projects/fmcomms8: Interconnect m_axi port for rx_xcvr 
Signed-off-by: LIacob106 <liviu.iacob@analog.com>
 2023-01-26 15:35:12 +02:00
Filip Gherman 4c1f68b119 vcu118_system_bd.tcl: Additional microblaze interrupt for VCU118 2023-01-17 13:31:16 +02:00
alin724 189624a655 ad7606x_fmc: Initial commit 2023-01-12 17:38:14 +02:00
LIacob106 19249b51db projects/fmcomms8: JESD support for 2, 4 TX_L and RX/ORX_L 
On zcu102 carrier.

Signed-off-by: LIacob106 <liviu.iacob@analog.com>
 2023-01-10 13:06:23 +02:00
sergiu arpadi 1b1cbfc8ef ad4110: Initial commit 2022-12-14 15:01:16 +02:00
Ionut Podgoreanu a3e1e6286b ad9081_fmca_ebz_x_band: Integrate the new TDD in project 2022-12-13 16:26:02 +02:00
Ionut Podgoreanu 5b95b6ce1f ad9081_fmca_ebz: Integrate the new TDD in project 2022-12-13 16:26:02 +02:00
AndrDragomir 8b9175a80c projects: Fix intermitent timing violation on a10soc 
adrv9009, dac_fmc_ebz, ad9081_fmca_ebz, fmcomms8:
Increased PLACEMENT_EFFORT_MULTIPLIER global parameter to 1.2 for increased quality of placement
 2022-12-13 14:21:24 +02:00
Sergiu Arpadi f64830364c ad469x: Use axi_pwm_gen; clean-up 
Replace axi_pulse_gen with axi_pmw_gen for softare support
considerations. Remove common/config.tcl and update project scripts
accordingly.
 2022-11-18 12:54:45 +02:00
Bogdan Luncan 72313df81f Updated the makefiles to build the projects in subdirectories based on the build parameters. 
Running 'make' will build the default project directly in the project folder (like it did before)
Running 'make RX_LANE_RATE=15 TX_LANE_RATE=15' will build the project inside the 'RXRATE15_TXRATE15' subdirectory.
Running 'make CFG=cfg/test_config.txt" will use the variables found inside the configuration file and build the project inside the 'test_config' subdirectory.
Running 'make clean' will clean the default project only.
Running 'make CFG=cfg/test_config.txt clean' will clean the 'testconfig' build.
Running 'make clean-all' will delete all the built configurations and libraries.

Note that the 'JESD' and 'LANE' words from the parameter names are stripped.

Signed-off-by: Bogdan Luncan <bogdan.luncan@analog.com>
 2022-11-14 09:38:42 +02:00
Filip Gherman 4e8c816d3f adi_board: Connnect phy_en_char_align only for 8B10B encoding 
In ad_xcvrcon procedure from adi_board, phy_en_char_align must be connected only when 8B10B encoding is used,
otherwise this signal does not exists in the JESD ip and will cause an error.

Signed-off-by: Filip Gherman <Filip.Gherman@analog.com>
 2022-11-01 14:24:31 +02:00
Laszlo Nagy fd0870352b ad9081_fmca_ebz_x_band:zcu102: X band project initial version 
HDL project for Stingray: X/Ku Band Phased Array Prototyping System
 2022-10-18 09:21:14 +03:00
AndreiGrozav fdb829347a ad9083 based projects: Expose JESD parameters 2022-10-12 17:50:17 +03:00
AndreiGrozav 67a5737fa1 ad9083_vna: Init commit 
Compatible with RevB
 2022-10-10 17:32:17 +03:00
laurent-19 1eb5f4985b projects/common: Add build files templates carriers. Modified Quartus Versions 
The build files are available for the following carriers:
* intel: a10gx, a10soc, c5soc, de10nano, s10soc
* xilinx: coraz7s, kc705, kcu105, vc707, vc709,
	  vck190, vcu118, vcu128, vmk180,
	  zc702, zc706, zcu102, zed

* Added Makefiles, system_constr.sdc, system_qsys intel
* Added Makefiles, system_bd, system_constr xilinx
* de10nano, c5soc: Changed quartus version from 20.1.1 to 21.1.0
  according to last commit update

Signed-off-by: laurent-19 <laurentiu.popa@analog.com>
 2022-10-05 10:47:21 +03:00
alin724 a4e052e986 cn0506: Update project's directory name in the README file 2022-10-03 10:30:24 +03:00
Liviu.Iacob 5350baffd0 adrv9009zu11eg/common/adrv9009zu11eg_bd: Add logic for TX_JESD_L=4 2022-10-03 10:27:33 +03:00
Liviu.Iacob a95536973f adrv9009/common/adrv9009_bd: Add logic for TX_JESD_L=2 2022-10-03 10:27:33 +03:00
Liviu.Iacob 6a583a8ace projects/fmcomms8: Expose jesd params, add support for TX_JESD_L=4 2022-10-03 10:27:15 +03:00
PopPaul2021 56691bd440 projects/cn0501: Updated with axi_ad7768 IP for Coraz7s 2022-09-30 12:56:57 +03:00
PopPaul2021 9caa15522a
The memory interconnect was moved from HP0 to HP1 on Coraz7s projects (#1023) 2022-09-29 15:14:57 +03:00
Iulia Moldovan 880f37555f ad719x_asdz/coraz7s: Initial commit 
* Added interrupt on RDYn on GPIO 32

Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
 2022-09-28 16:30:42 +03:00
Stanca Pop 56290a609d ad4630_fmc: Match project name with folder name 2022-09-26 15:37:49 +03:00
Stanca Pop d2d32458f4 ad9783_ebz: Match project name with folder name 2022-09-26 15:37:49 +03:00
LIacob106 3e297f54dd projects/adrv9009zu11eg: expose jesd params to make and add FMCOMMS8 parameter 
Expose JESD parameters to make.
Add FMCOMMS8 parameter.
Changed the name of the observation path to match the rest of the repo.
Replace old dac_data_width formula with a more generic one.
 2022-09-26 14:26:31 +03:00
PopPaul2021 8a77d4fb05
coraz7s: Memory interconnect fix (#1014) 2022-09-23 14:58:43 +03:00
Iulia Moldovan 474b8d5bed cn0577/zed: Update xdc to diff_term true. Disable csn in system_top 
* Update xdc to use diff_term true instead of diff_term 1
 * Generated xdc using adi_fmc_constr_generator.tcl
 * Make CSN to be inactive
 * Cosmetic changes also

Signed-off-by: Iulia Moldovan <iulia.moldovan@analog.com>
 2022-09-21 09:42:40 +03:00
laurent-19 6b94259a52 projects/common: Add system_top _project templates 
Signed-off-by: laurent-19 <laurentiu.popa@analog.com>

projects/common: Correct code and modify according to guidelines

* Added spacing to ports declaration
* Corrected coding mistakes/misspelling
* Modified/added variables names
* Added seetings (intel) and removed specific optimization settings
* Added assignments to unassigned pins (gpios)

Signed-off-by: laurent-19 <laurentiu.popa@analog.com>

projects/common: Correct/Add missing wrapper ports and iobufs

* Added port in wrapper (mainly spi) according to base design file
* Added instances of iobufs where missing
* Corrected gpio assignments or added missing ones
* Corrected minor guidelines mistakes

Signed-off-by: laurent-19 <laurentiu.popa@analog.com>

ac701/system_top.v: Change top based on previous projects

 * Looked at fmcomms1, fmcomms2 from hdl_2016_r1 and datasheet

Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>

projects/common: Modify templates to build without errors

* Changed path for adi_env.tcl
* Moved adi_project command before assign intel
* Removed unnecessary spi signals
* Added spi ports with default logic
* a10soc: Removed pl-ddr signals and ports
* ac701: system_bd: Modified mdio interface
	 system_project: Added adi_board, adiobuf sourcing
	 system_top: Removed hdmi, i2c, fanpwm, spdif ports
		     according to base design
* c5soc: Added version settings
	 Removed unused gpios
* microzed: system_bd: Enabled RTS1 to use FCLK
	    system_top: Removed hdmi, i2c, unused gpios
* vc709: Separated input from ouput gpio, according to bd
	 Removed unnecessary ports

Signed-off-by: laurent-19 <laurentiu.popa@analog.com>

projects/common: Delete microzed vmk_es templates

* Removed hp0 interconnect from cora base design
* Added extra line to files de10nano

Signed-off-by: laurent-19 <laurentiu.popa@analog.com>
 2022-09-20 17:00:49 +03:00
AndrDragomir 7cde7cd048 projects/scripts: Add fmc constraints generator script 
Using the script:
  - make sure that the eval board in use has a common fmc connection file.
  if you created a new one, it should be saved as &project_name_fmc.txt inside
  &project_name/common
  - open a tcl terminal, either inside or outside the project
  - make sure your current directory is &hdl_repo/projects/&project_name/&carrier
  - source the script found at &hdl_repo/project/scripts/fmc_constr_generator.tcl
  - call gen_fmc_constr $parameter_1 $parameter_2:
      - in case of only one fmc port on the carrier call without any parameters
      - if there are two fmc ports on the carrier and you want to use only one,
      the first parameter should contain an indication (fmc_lpc/hpc, fmc0/1, etc.)
      - if there are two fmc ports on the carrier and you want to use both, then
      both parameters should contain an indication
  - the constraints file will be generated in the current directory

Signed-off-by: AndrDragomir <andrei.dragomir@analog.com>
 2022-09-20 14:11:08 +03:00
AndrDragomir 72378a6d4a projects: Add fmc connection files for eval boards 
Creating a new eval board fmc file:
  - docs: Open FMC_eval_board_template.xlsx
  - follow the instructions on the first sheet
 2022-09-20 14:11:08 +03:00
AndrDragomir 72cf8f9b5d projects/common: Add fmc connection files for every platform 2022-09-20 14:11:08 +03:00
LIacob106 158c10df34 projects: starndadize the jesd make parameters 2022-09-13 11:53:21 +03:00
Laszlo Nagy d20e604864 ad9082_fmca_ebz/zcu102: Make TPL width overwritable 2022-08-25 12:35:42 +03:00
Laszlo Nagy e332409610 ad9081_fmca_ebz: Make TPL width overwritable 2022-08-25 12:35:42 +03:00
Ionut Podgoreanu 5a06f186ae ad9081_fmca_ebz/common: Use the script to compute the TPL width 2022-08-25 12:35:42 +03:00
AndreiGrozav f955fbc6c0 adi_pd.tcl: Fix sysid branch string 
For some newer versions of git where by default color.ui=always.
The colored string captured can result in some special characters
(ASCI escape codes for coloring the terminal output) before and after the string.
e.g:
$ git branch > test.txt
$ vim test.txt
"
* ^[[32mmaster^[[m
  dev_new_device^[[m"

The above escape codes will mess up a terminals color scheme  when this
information is read from sysid and displayed on a terminal.

Use --no-color flag to fix this issue.
 2022-08-25 11:36:25 +03:00
Iulia Moldovan 388611866a projects: Fix some Makefiles 
* ad9082_fmca_ebz/vcu118
 * dac_fmc_ebz/vcu118

Signed-off-by: Iulia Moldovan <iulia.moldovan@analog.com>
 2022-08-25 09:35:55 +03:00
ladace cf4e1b79cf
scripts:adi_env: Change the default version of Quartus Standard to 21.1 (#996) 
New version of Quartus Standard for de10nano and sockit  was changed
to 21.1.

Signed-off-by: Liviu Adace <liviu.adace@analog.com>

Signed-off-by: Liviu Adace <liviu.adace@analog.com>
 2022-08-24 17:01:06 +03:00
PopPaul2021 cc18f90579
Added axi_ad7768 IP Core (#989) 
* projects/ad7768evb: Initial commit with axi_ad7768 IP

* library/axi_ad7768: Initial commit for AD7768/AD7768-4
 2022-08-24 16:57:14 +03:00
ladace 4307e3071f
scripts:adi_env: Change the default version of Quartus Pro to 21.4 (#988) 
New version of Quartus Pro for A10SOC, A10GX and S10SOC was changed
to 21.4. Is known that some projects will not build anymore due to
timming violations.
 2022-08-18 17:08:29 +03:00
Iulia Moldovan dde37124a4 scripts: Update Vivado version to 2021.2 
Signed-off-by: Iulia Moldovan <iulia.moldovan@analog.com>
 2022-08-18 15:41:58 +03:00
PopPaul2021 0595f93452
AD777x support for ZedBoard and DE10Nano (#937) 
* library/common: Ad adc_status_header, adc_crc_err and adc_crc_enable.

* library/axi_ad777x: Initial commit for Xilinx and Intel

* projects/ad777x_ardz: Initial commit for ZedBoard and DE10Nano
 2022-08-10 11:29:05 +03:00
Iacob_Liviu 482f0489a3 scripts: Merge adi_env.tcl into a single file 
Move the new adi_env.tcl file from hdl/projects/scripts into hdl/scrips
 2022-08-08 13:52:54 +03:00
Laszlo Nagy d48b1bcdce ad9081_fmca_ebz/vck190: Expose ref clock parameter 2022-08-04 09:52:57 +03:00
Laszlo Nagy 78333b2c90 ad9081_fmca_ebz/common/versal_transceiver: Separate lane rates for Tx and Rx 2022-08-04 09:52:57 +03:00
Laszlo Nagy 3379dd3bdb ad9082_fmca_ebz/zcu102: Make JESD_MODE overwritable 2022-08-04 09:50:18 +03:00
Liviu.Iacob 54a22d036c adi_pd.tcl: Fix git_clean_string logic 2022-08-02 17:11:49 +03:00
Sergiu Arpadi 94c4a291a7 cn0561_coraz7s: Fix gpio connections 2022-08-02 17:11:19 +03:00
Sergiu Arpadi bb3027995a sysid: Add sysid support for de10nano 
make adv7513

make 0540
 2022-08-02 14:15:34 +03:00
Laszlo Nagy c748b3bbc7 ad9082_fmca_ebz/zc706: Fix parameters 
Match default parameters for L=4 M=8 mode with 10Gbps.
The L=8 M=4 would require lane rate of 15Gbps that is not supported on
zc706.
 2022-08-01 16:40:03 +03:00
Laszlo Nagy aae7971689 ad9082_fmca_ebz/vcu118: Fix default lane rate parameter 2022-08-01 16:40:03 +03:00
Laszlo Nagy aed7032e0c ad9082_fmca_ebz/zcu102: Fix default lane rate parameter 2022-08-01 16:40:03 +03:00
Laszlo Nagy 2b274f945f ad9081_fmca_ebz: Reset cpack with Rx data offload 2022-08-01 12:47:26 +03:00
Filip Gherman d48ab915a5 vcu128: Connect sys_mb_rstgen/ext_reset_in accordingly 
Signed-off-by: Filip Gherman <Filip.Gherman@analog.com>
 2022-07-29 20:05:08 +03:00
alin724 6aa899f161 scripts/adi_project_xilinx.tcl: Add new constraints file support 2022-07-20 14:36:04 +03:00
alin724 9864d96096 Merge CN0506 projects into a parameterized one 2022-07-20 14:36:04 +03:00
Iulia Moldovan 961ebe0cc2 projects: Update .v files according to guideline 
Deleted lines after endmodule and consecutive empty lines.
Modified parentheses, extra spaces.
Fixed indentation.
Fixed parameters list to be each parameter on its line.

Signed-off-by: Iulia Moldovan <iulia.moldovan@analog.com>
 2022-06-28 18:06:56 +03:00
Laszlo Nagy 171daab8f2 ad9081_fmca_ebz: a10soc: Update resistor change comment 
A board rework is required so the clocks, chip selects or sync signal reach the part correctly.  Without this the link will not come up.
 2022-06-21 14:19:58 +03:00
Laszlo Nagy a8174ac038 ad_quadmxfe1_ebz/vcu118/system_project.tcl: Update comments 
Update PLL selection docs.
 2022-06-08 15:35:47 +03:00
ladace 6525a37375
ad_fmclidar1_ebz:a10soc Fixed problems with SPI communication with AD9094 (#951) 
Now CPH and CPOL are set to 1, also the SPI clock is set to 10MHz

Signed-off-by: Liviu Adace <liviu.adace@analog.com>
 2022-06-06 13:00:45 +03:00
PopPaul2021 4f4825a3df
projects:daq2:common: fix adi_tpl_jesd204_rx_create error. (#952) 
(\ character has to be removed or a blank line inserted before ad_ip_parameter)
Fix for : 0b8585a6f commit.
 2022-06-06 08:53:07 +03:00
PopPaul2021 0b8585a6f1
PN mismatch DAQ2, DAQ3 and FMCJESDADC1 fix (#950) 
The AD9680 is a dual 14-bit ADC.
Software sets the output format to offset binary before performing the PN tests.
 2022-06-02 14:09:36 +03:00
Ionut Podgoreanu f957d81db1 ad9083_evb_bd: Connect util_ad9083_rx_cpack reset to adc_rst 2022-05-27 09:20:09 +03:00
Filip Gherman 1ae375f4fb ad_quadmxfe1_ebz/vcu118: Change drp clock source used for jesd204_phy 
- Added an utility buffer in order to generate the 50Mhz DRP clock.
- 'addn_ui_clockout4' will be used to generate the higher frequency 'sys_mb' clock for Microblaze.

Signed-off-by: Filip Gherman <Filip.Gherman@analog.com>
 2022-05-27 00:48:34 +03:00
Filip Gherman 5ad9dfd6c0 vcu118: Increase Microblaze performance and clock frequency 
Increased the Microblaze performance for the VCU118 carrier:
- Increased the size of Instruction Cache and Data Cache to 64kB

Increased the Microblaze clock frequency:
- Using the DDR4 Controller to generate a new sys_mb_clk of 214 MHz to drive all the Microblaze interfaces at higher frequencies

Signed-off-by: Filip Gherman <Filip.Gherman@analog.com>
 2022-05-27 00:48:17 +03:00
Laszlo Nagy bdd5686e95 ad9081_fmca_ebz/a10soc: Make second sync CMOS and GPIO controllable 2022-05-26 09:13:05 +03:00
Laszlo Nagy a2da965391 ad9081_fmca_ebz/vck190: Make second sync CMOS and GPIO controllable 2022-05-26 09:13:05 +03:00
Laszlo Nagy 20b89ddd99 ad9081_fmca_ebz/vcu128: Make second sync CMOS and GPIO controllable 2022-05-26 09:13:05 +03:00
Laszlo Nagy b3d231e569 ad9081_fmca_ebz/zc706: Make second sync CMOS and GPIO controllable 2022-05-26 09:13:05 +03:00
ladace ab5c344c89
ad_fmclidar1_ebz:a10soc Fixed SPI communication on Arria 10 (#947) 
Signed-off-by: Liviu Adace <liviu.adace@analog.com>
 2022-05-24 12:44:03 +03:00