a0f4adabd0
avl_adxcvr: Fix core clock bridge frequency
...
The clock bridge expects the clock rate to be specified in Hz, but
$m_coreclk_frequency is in MHz. Do the appropriate conversion.
Nothing seems to rely on the clock bridge reporting the correct frequency
at the moment, so this is only a cosmetic change.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-07-28 15:11:08 +02:00
354b311f3d
library/avl_adxcvr: fpll fixes
2017-06-21 15:26:00 -04:00
9464f342cf
avl_adxcvr: remove arria v support
2017-06-15 11:36:14 -04:00
173837f5b2
altera- altera ip interfaces has no consistency
2017-06-09 16:21:44 -04:00
034aa7c1ee
altera 16.1- recommends using fpll for dedicated low skew clock routing
2017-06-08 10:50:52 -04:00
ebeebdddf0
altera- infer latest versions
2017-05-12 13:40:14 -04:00
c728299e71
altera- default to latest version
2017-05-12 13:25:17 -04:00
0b58a2a1db
avl_adxcvr- sysclk frequency
2016-11-09 09:21:07 -05:00
48ee720901
avl_adxcvr- a5 requires single transceiver controller
2016-11-08 15:20:01 -05:00
ee9c8b884d
avlxcvr- add arria v support
2016-11-04 15:01:19 -04:00
21545ee83f
avl_adxcvr- ip/phy split
2016-09-12 14:57:50 -04:00
4ae084ee32
avl_adxcvr- compile fixes
2016-09-01 10:06:28 -04:00
b7ea2efa87
altera- xcvr cores
2016-08-29 15:18:48 -04:00
Lars-Peter Clausen
Rejeesh Kutty