de4fe30238
library: Match s_axi_{awaddr,araddr} signal width to peripheral memory map size
...
The external s_axi_{awaddr,araddr} signals that are connect to the core
have their width set according to the specified size of the register map.
If the s_axi_{awaddr,araddr} signal of the core is wider (as it currently
is for many cores) the MSBs of those signals are left unconnected, which
generates a warning.
To avoid this make sure that the signal width matches the declared register
map size.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-08-01 15:21:25 +02:00
84b2ad51e2
license: Add some clarification to the header license
2017-05-31 18:18:56 +03:00
85ebd3ca01
license: Update license terms in hdl source files
...
Fix a few gramatical error, fix the path of the top level license
files.
2017-05-29 09:55:41 +03:00
10898d6618
constraints: Split the regmap CDC constraint into separate file
2017-05-25 15:12:16 +03:00
9055774795
all: Update license for all hdl source files
...
All the hdl (verilog and vhdl) source files were updated. If a file did not
have any license, it was added into it. Files, which were generated by
a tool (like Matlab) or were took over from other source (like opencores.org),
were unchanged.
New license looks as follows:
Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
Each core or library found in this collection may have its own licensing terms.
The user should keep this in in mind while exploring these cores.
Redistribution and use in source and binary forms,
with or without modification of this file, are permitted under the terms of either
(at the option of the user):
1. The GNU General Public License version 2 as published by the
Free Software Foundation, which can be found in the top level directory, or at:
https://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html
OR
2. An ADI specific BSD license as noted in the top level directory, or on-line at:
https://github.com/analogdevicesinc/hdl/blob/dev/LICENSE
2017-05-17 11:52:08 +03:00
41e25e7c96
Add missing ad_serdes_out interface ports
2017-05-16 19:35:24 +03:00
c728299e71
altera- default to latest version
2017-05-12 13:25:17 -04:00
0e1e507541
axi dac cores: Add missing ports to up_dac_common instance
2017-05-12 13:37:34 +03:00
cfd4e006b3
hdlmake updates
2017-04-25 15:46:26 -04:00
1c23cf4621
all: Update verilog files to verilog-2001
2017-04-13 11:59:55 +03:00
c1bdfca4c3
library: Delete all adi_ip_constraint process call
2017-04-06 12:36:47 +03:00
fd56b5a6d3
axi_ad9122: Update constraint files
2017-03-31 10:13:42 +03:00
a57fb5f82f
library/ad9122- constraints clean-up
2017-02-02 14:21:41 -05:00
596d0fa3fb
axi_ad9122: Add a constraint for a false path
2016-12-16 12:07:40 +00:00
8ebc8fe4e2
updated makefiles
2016-12-09 23:06:41 +02:00
b0a5be8565
axi_ad9122: Add loaden port for altera support
2016-12-06 15:24:20 +02:00
cedca30cd6
axi_ad9122: Update hw tcl script for altera
2016-12-06 15:24:19 +02:00
3f3606d318
axi_ad9122: Add Altera support for the core
2016-10-24 11:43:12 +03:00
a505d304af
Add up_dac_common missing connections
2016-10-12 13:20:26 +03:00
43ee917d53
Add up_dac_channel missing connections
2016-10-12 13:20:26 +03:00
f6c7aa9005
library- dac parameter changes
2016-09-23 16:15:59 -04:00
64cd7dc002
axi_ad9122: Update core to the new DRP interface
2016-09-21 16:09:55 +03:00
0cd608a7e2
lib_refactoring: Update Make files
2016-08-08 16:38:38 +03:00
df36902713
lib_refactoring: Fix path of the IO macros
2016-08-08 15:07:19 +03:00
d60bce654c
Makefiles: Updated Makefiles so they run correctly with gnuwin32 tools
2016-08-05 15:16:04 +03:00
6ebb32a194
library axi-slave missing protection signal added
2016-07-22 12:54:27 -04:00
c293c04634
hdl make updates
2016-06-01 13:53:09 -04:00
74408881c6
axi_ad9122: optional clock out control
2016-03-22 12:50:59 -04:00
8ecf5edaf8
ad9122- pat modes
2016-03-14 11:14:29 -04:00
9d2b8809df
Makefiles: Updated Makefiles
2015-10-23 10:44:27 +03:00
5347c058df
axi_ad9122: Updated core with latest constraints
2015-09-16 15:48:33 +03:00
7b858bc5ad
Revert commit 6b99ce
...
Revert 6b99ce2482
2015-08-26 13:48:28 +03:00
6b99ce2482
library: Added common constraints for all cores. Commented code that needs to be updated to 2015.2
2015-08-20 18:17:38 +03:00
57cfb7cfb1
hdl/library: Update the IP parameters
...
The following IP parameters were renamed:
PCORE_ID --> ID
PCORE_DEVTYPE --> DEVICE_TYPE
PCORE_IODELAY_GROUP --> IO_DELAY_GROUP
CH_DW --> CHANNEL_DATA_WIDTH
CH_CNT --> NUM_OF_CHANNELS
PCORE_BUFTYPE --> DEVICE_TYPE
PCORE_ADC_DP_DISABLE --> ADC_DATAPATH_DISABLE
CHID --> CHANNEL_ID
PCORE_DEVICE_TYPE --> DEVICE_TYPE
PCORE_MMCM_BUFIO_N --> MMCM_BUFIO_N
PCORE_SERDES_DDR_N --> SERDES_DDR_N
PCORE_DAC_DP_DISABLE --> DAC_DATAPATH_DISABLE
DP_DISABLE --> DATAPATH_DISABLE
PCORE_DAC_IODELAY_ENABLE --> DAC_IODELAY_ENABLE
C_BIG_ENDIAN --> BIG_ENDIAN
C_M_DATA_WIDTH --> MASTER_DATA_WIDTH
C_S_DATA_WIDTH --> SLAVE_DATA_WIDTH
NUM_CHANNELS --> NUM_OF_CHANNELS
CHANNELS --> NUM_OF_CHANNELS
PCORE_4L_2L_N -->QUAD_OR_DUAL_N
C_ADDRESS_WIDTH --> ADDRESS_WIDTH
C_DATA_WIDTH --> DATA_WIDTH
C_CLKS_ASYNC --> CLKS_ASYNC
PCORE_QUAD_DUAL_N --> QUAD_DUAL_N
NUM_CS --> NUM_OF_CS
PCORE_DAC_CHANNEL_ID --> DAC_CHANNEL_ID
PCORE_ADC_CHANNEL_ID --> ADC_CHANNEL_ID
PCORE_CLK0_DIV --> CLK0_DIV
PCORE_CLK1_DIV --> CLK1_DIV
PCORE_CLKIN_PERIOD --> CLKIN_PERIOD
PCORE_VCO_DIV --> VCO_DIV
PCORE_Cr_Cb_N --> CR_CB_N
PCORE_VCO_MUL --> VCO_MUL
PCORE_EMBEDDED_SYNC --> EMBEDDED_SYNC
PCORE_AXI_ID_WIDTH --> AXI_ID_WIDTH
PCORE_ADDR_WIDTH --> ADDRESS_WIDTH
DADATA_WIDTH --> DATA_WIDTH
NUM_OF_NUM_OF_CHANNEL --> NUM_OF_CHANNELS
DEBOUNCER_LEN --> DEBOUNCER_LENGTH
ADDR_WIDTH --> ADDRESS_WIDTH
C_S_AXIS_REGISTERED --> S_AXIS_REGISTERED
Cr_Cb_N --> CR_CB_N
ADDATA_WIDTH --> ADC_DATA_WIDTH
BUFTYPE --> DEVICE_TYPE
NUM_BITS --> NUM_OF_BITS
WIDTH_A --> A_DATA_WIDTH
WIDTH_B --> B_DATA_WIDTH
CH_OCNT --> NUM_OF_CHANNELS_O
M_CNT --> NUM_OF_CHANNELS_M
P_CNT --> NUM_OF_CHANNELS_P
CH_ICNT --> NUM_OF_CHANNELS_I
CH_MCNT --> NUM_OF_CHANNELS_M
4L_2L_N --> QUAD_OR_DUAL_N
SPI_CLK_ASYNC --> ASYNC_SPI_CLK
MMCM_BUFIO_N --> MMCM_OR_BUFIO_N
SERDES_DDR_N --> SERDES_OR_DDR_N
CLK_ASYNC --> ASYNC_CLK
CLKS_ASYNC --> ASYNC_CLK
SERDES --> SERDES_OR_DDR_N
GTH_GTX_N --> GTH_OR_GTX_N
IF_TYPE --> DDR_OR_SDR_N
PARALLEL_WIDTH --> DATA_WIDTH
ADD_SUB --> ADD_OR_SUB_N
A_WIDTH --> A_DATA_WIDTH
CONST_VALUE --> B_DATA_VALUE
IO_BASEADDR --> BASE_ADDRESS
IO_WIDTH --> DATA_WIDTH
QUAD_DUAL_N --> QUAD_OR_DUAL_N
AXI_ADDRLIMIT --> AXI_ADDRESS_LIMIT
ADDRESS_A_DATA_WIDTH --> A_ADDRESS_WIDTH
ADDRESS_B_DATA_WIDTH --> B_ADDRESS_WIDTH
MODE_OF_ENABLE --> CONTROL_TYPE
CONTROL_TYPE --> LEVEL_OR_PULSE_N
IQSEL --> Q_OR_I_N
MMCM --> MMCM_OR_BUFR_N
2015-08-19 14:11:47 +03:00
b84afcdcd1
Merge branch 'master' into dev
...
Conflicts:
library/Makefile
library/axi_ad6676/axi_ad6676_ip.tcl
library/axi_ad9122/axi_ad9122_core.v
library/axi_ad9122/axi_ad9122_ip.tcl
library/axi_ad9144/axi_ad9144_ip.tcl
library/axi_ad9152/axi_ad9152_ip.tcl
library/axi_ad9234/axi_ad9234_ip.tcl
library/axi_ad9250/axi_ad9250_hw.tcl
library/axi_ad9250/axi_ad9250_ip.tcl
library/axi_ad9361/axi_ad9361.v
library/axi_ad9361/axi_ad9361_dev_if_alt.v
library/axi_ad9361/axi_ad9361_ip.tcl
library/axi_ad9361/axi_ad9361_rx_channel.v
library/axi_ad9361/axi_ad9361_tdd.v
library/axi_ad9361/axi_ad9361_tx_channel.v
library/axi_ad9625/axi_ad9625_ip.tcl
library/axi_ad9643/axi_ad9643_channel.v
library/axi_ad9643/axi_ad9643_ip.tcl
library/axi_ad9652/axi_ad9652_channel.v
library/axi_ad9652/axi_ad9652_ip.tcl
library/axi_ad9671/axi_ad9671_constr.xdc
library/axi_ad9671/axi_ad9671_ip.tcl
library/axi_ad9680/axi_ad9680_ip.tcl
library/axi_ad9739a/axi_ad9739a_ip.tcl
library/axi_dmac/axi_dmac_constr.sdc
library/axi_hdmi_tx/axi_hdmi_tx_ip.tcl
library/axi_jesd_gt/axi_jesd_gt_constr.xdc
library/axi_jesd_gt/axi_jesd_gt_ip.tcl
library/axi_mc_speed/axi_mc_speed_constr.xdc
library/common/ad_gt_channel_1.v
library/common/ad_gt_common_1.v
library/common/ad_gt_es.v
library/common/ad_iqcor.v
library/common/ad_jesd_align.v
library/common/ad_rst.v
library/common/altera/ad_xcvr_rx_rst.v
library/common/up_adc_common.v
library/common/up_axis_dma_rx.v
library/common/up_axis_dma_tx.v
library/common/up_clkgen.v
library/common/up_clock_mon.v
library/common/up_dac_common.v
library/common/up_gt.v
library/common/up_hdmi_tx.v
library/common/up_tdd_cntrl.v
library/common/up_xfer_cntrl.v
library/common/up_xfer_status.v
library/util_cpack/util_cpack.v
library/util_cpack/util_cpack_ip.tcl
library/util_dac_unpack/util_dac_unpack_hw.tcl
library/util_jesd_align/util_jesd_align.v
library/util_jesd_xmit/util_jesd_xmit.v
library/util_upack/util_upack_ip.tcl
library/util_wfifo/util_wfifo.v
library/util_wfifo/util_wfifo_constr.xdc
library/util_wfifo/util_wfifo_ip.tcl
projects/arradio/c5soc/system_bd.qsys
projects/common/vc707/vc707_system_bd.tcl
projects/common/zc706/zc706_system_plddr3.tcl
projects/daq2/a10gx/Makefile
projects/daq2/a10gx/system_bd.qsys
projects/daq3/common/daq3_bd.tcl
projects/daq3/zc706/system_bd.tcl
projects/fmcjesdadc1/a5gt/Makefile
projects/fmcjesdadc1/a5gt/system_bd.qsys
projects/fmcjesdadc1/a5gt/system_constr.sdc
projects/fmcjesdadc1/a5gt/system_top.v
projects/fmcjesdadc1/a5soc/system_bd.qsys
projects/fmcjesdadc1/common/fmcjesdadc1_bd.tcl
projects/fmcomms1/ac701/system_bd.tcl
projects/fmcomms1/common/fmcomms1_bd.tcl
projects/fmcomms1/kc705/system_bd.tcl
projects/fmcomms1/vc707/system_bd.tcl
projects/fmcomms1/zc702/system_bd.tcl
projects/fmcomms1/zc702/system_top.v
projects/fmcomms1/zc706/system_bd.tcl
projects/fmcomms1/zc706/system_top.v
projects/fmcomms1/zed/system_bd.tcl
projects/fmcomms1/zed/system_top.v
projects/fmcomms2/ac701/system_constr.xdc
projects/fmcomms2/common/fmcomms2_bd.tcl
projects/fmcomms2/kc705/system_constr.xdc
projects/fmcomms2/kc705/system_top.v
projects/fmcomms2/mitx045/system_top.v
projects/fmcomms2/rfsom/system_constr.xdc
projects/fmcomms2/rfsom/system_top.v
projects/fmcomms2/vc707/system_top.v
projects/fmcomms2/zc706/system_bd.tcl
projects/fmcomms2/zc706/system_constr.xdc
projects/fmcomms2/zc706/system_top.v
projects/fmcomms2/zed/system_top.v
projects/imageon/zc706/system_constr.xdc
projects/motcon2_fmc/common/motcon2_fmc_bd.tcl
projects/motcon2_fmc/zed/system_constr.xdc
projects/motcon2_fmc/zed/system_top.v
projects/usdrx1/a5gt/Makefile
projects/usdrx1/a5gt/system_bd.qsys
projects/usdrx1/common/usdrx1_bd.tcl
Conflicts were resolved using 'Mine' (/dev).
2015-08-17 15:15:58 +03:00
46fa91d5be
Makefile: Update Make files
2015-07-03 18:08:57 +03:00
c372064302
Add .gitattributes file
...
Add .gitattributes file which sets up the eol encoding handling. This will
make sure that we get a uniform eol encoding across different operating
systems.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-07-01 18:43:51 +02:00
6862655b0d
Add .gitattributes file
...
Add .gitattributes file which sets up the eol encoding handling. This will
make sure that we get a uniform eol encoding across different operating
systems.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-26 11:07:10 +02:00
fcc185d769
Makefile: Updated makefiles
...
- removed up_drp_control, up_delay_control dependencies where not needed
- added axi_jesd_gt core in the library makefile
- fixed timing tcl dependency for altera projects
2015-06-25 14:59:34 +03:00
5e4f572092
axi_ad9122: Fixed constraints
2015-06-10 10:56:03 +03:00
ded0dd5dbe
axi_ad9122: fixed constraints, removed unneded drp reset
2015-06-08 17:45:14 +03:00
91b0f70972
library: remove drp cntrl
2015-06-02 09:58:57 -04:00
c6ebab7393
library- drp moved to up clock
2015-06-01 13:39:26 -04:00
e918588a4b
library: remove axi-min-size parameter
2015-05-19 13:07:48 -04:00
d950f5ffcd
axi_ad9122: Updated constraints
2015-04-27 11:18:52 +03:00
e7ce2b200d
axi_ad9122: Added CDC and reset constraints
2015-04-23 10:17:53 +03:00
dc2b37bd0c
Makefile: Added top level Makefile. Modified behavior of clean and clean-all
...
Clean ran for a project will clean only the project files.
Clean-all ran for a project will clean also the library files on which the project depends.
The clean commands will only remove specific files and directories.
The top Makefile allows several options(per suggestion from jameyhicks):
make fmcomms1.zed will run "make all" in projects/fmcomms1/zed/
make clean will run "make clean" for all the projects
make clean-all will run "make clean" for all the projects and libraries
make lib will run "make all" for the library files
2015-04-17 17:22:38 +03:00
374f82e7de
makefiles: The clean command for library won't remove the xml files, except for component.xml.
...
Updated also the dmac dependencies
2015-04-16 11:53:27 +03:00
5f8e9a74ea
makefile: updated
2015-04-07 16:32:01 -04:00
f79a152958
Makefiles: updated all makefiles adding clean functionality
2015-04-03 11:57:54 +03:00
Lars-Peter Clausen
Istvan Csomortani
AndreiGrozav
Rejeesh Kutty
Adrian Costina
Shrutika Redkar