68461110aa
Replace link in license header from master to main
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Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
2024-01-16 16:48:45 +02:00
c9a7d4d927
Add copyright and license to .tcl, .ttcl files
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Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
2023-07-25 15:22:26 +03:00
1cac2d82e1
Add copyright and license to .xdc files
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Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
2023-07-25 11:03:02 +03:00
28c06d505f
Add/edit copyright and license for .v, .sv files
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Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
2023-07-11 15:17:41 +03:00
db94628cc6
library & projects: Update Makefiles
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Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
2023-01-27 11:54:05 +02:00
72313df81f
Updated the makefiles to build the projects in subdirectories based on the build parameters.
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Running 'make' will build the default project directly in the project folder (like it did before)
Running 'make RX_LANE_RATE=15 TX_LANE_RATE=15' will build the project inside the 'RXRATE15_TXRATE15' subdirectory.
Running 'make CFG=cfg/test_config.txt" will use the variables found inside the configuration file and build the project inside the 'test_config' subdirectory.
Running 'make clean' will clean the default project only.
Running 'make CFG=cfg/test_config.txt clean' will clean the 'testconfig' build.
Running 'make clean-all' will delete all the built configurations and libraries.
Note that the 'JESD' and 'LANE' words from the parameter names are stripped.
Signed-off-by: Bogdan Luncan <bogdan.luncan@analog.com>
2022-11-14 09:38:42 +02:00
482f0489a3
scripts: Merge adi_env.tcl into a single file
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Move the new adi_env.tcl file from hdl/projects/scripts into hdl/scrips
2022-08-08 13:52:54 +03:00
961ebe0cc2
projects: Update .v files according to guideline
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Deleted lines after endmodule and consecutive empty lines.
Modified parentheses, extra spaces.
Fixed indentation.
Fixed parameters list to be each parameter on its line.
Signed-off-by: Iulia Moldovan <iulia.moldovan@analog.com>
2022-06-28 18:06:56 +03:00
591a23156b
Makefiles: Update header with the appropriate license
2021-09-16 16:50:53 +03:00
fec4137046
ad400xx_fmc: Parametrize board select, sampling rate and adc resolution
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fix comments
2021-09-01 15:03:10 +03:00
3041e77659
ad40xx/zed: Update constraints
2021-02-04 11:04:32 +02:00
6f2f2b8626
makefile: Regenerate make files
2021-01-20 01:02:56 +02:00
da61515d41
ad40xx: Fix bd.tcl script
2021-01-20 01:02:56 +02:00
acbbd4636a
sysid: Upgrade framework, header/ip are now at 2/1.1.a
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Unify tcl scripts; rename adi_pd_intel.tcl to adi_pd.tcl
add git branch to internal use area; update log prints;
update xilixn projects; fix cn0506 sysid script;
2021-01-20 01:02:56 +02:00
b989ba36d1
axi_spi_engine: Fix util_axis_fifo instance related issues
2021-01-08 12:29:26 +02:00
9093a8c428
library: Move ad_iobuf to the common library, as it's not Xilinx specific
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Updated all system_project and Makefiles
2020-11-02 16:13:35 +02:00
d8ab27b2af
sysid: Remove cstring init string
2020-09-30 19:12:24 +03:00
40772a8b2c
ad40xx_fmc/zed: Fix constraints, to avoid critical warnings in synthesis
2020-09-15 13:08:39 +03:00
05c20af988
Merge pull request #430 from analogdevicesinc/update_tcl
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Rename projects for consistency
2020-02-06 16:32:40 +02:00
fa259c7975
ad40xx: Fix a typo
2020-01-10 10:20:06 +02:00
9497b1cace
ad40xx: Remove redundant upscaler IP, Add timing constraints
2020-01-09 11:32:31 +02:00
aa5fdf903e
Makefile: Update makefiles
2019-08-26 16:58:01 +03:00
0680e44330
system_id: deployed ip
2019-08-06 16:53:11 +03:00
a589753d92
project/scripts: Rename adi_project.tcl to adi_project_xilinx.tcl
2019-06-29 06:53:51 +03:00
43725429ac
adi_project: Rename the process adi_project_xilinx to adi_project
2019-06-29 06:53:51 +03:00
ba4a915af0
ad40xx/zed: fixed system_bd
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spi_engine_execution: fixed sdo default
2019-06-28 11:18:29 +03:00
cf9d0814d5
ad40xx/zed: Place all the SPI registers near IOB
2019-06-28 11:18:29 +03:00
10e1abc22f
ad40xx_fmc/zed: Delete IOB TRUE constraints
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Vivado can not apply the IOB TRUE constraint to only one bit of a
registers. So these constraints will generate several CRITICAL WARNING.
Taking into consideration the maximum used frequencies and current
architecture these constraints are not critical.
2019-06-28 11:18:29 +03:00
9ab88f1200
ad40xx: Initial commit
2019-06-28 11:18:29 +03:00
Iulia Moldovan
Bogdan Luncan
Iacob_Liviu
Adrian Costina
Istvan Csomortani
Sergiu Arpadi
StancaPop
Stanca Pop