With the new make -jX support flock is used but shells out sometimes.
This assumes a bash like shell which isn't always the case. This fix
forces flock to use sh.
Signed-off-by: Travis F. Collins <travis.collins@analog.com>
Lattice tools give error for using blocking assignments at one side
and non blocking in the other.
Signed-off-by: Villyam <Vilmoscsaba.Jozsa@analog.com>
docs: Add JESD204 documentation in sphinx
Fixes several semantic issues from the original doc in wiki
Implicit path to library when the doc is hierarchically coherent with the
library.
Signed-off-by: Carlos Souza <carlos.souza@analog.com>
Co-authored-by: Jorge Marques <jorge.marques@analog.com>
Revert AXI bus signals back to upper case on SPI Engine Offload IP,
changed on e2ca5a991a.
Fixup signals from sd*_data_* to sd*_* for spi_engine_ctrl interface.
Non-breaking mistake, but added warnings to the IP.
Signed-off-by: Jorge Marques <jorge.marques@analog.com>
* SPI Engine: Add registers for Offload memory and FIFO sizes
Adds registers at dword 0x04 and 0x05, respectively allowing software
to get the sizes of the Offload Module memories (command and sdo) or
the sizes of the FIFOs on the AXI regmap.
Signed-off-by: Laez Barbosa <laez.barbosa@analog.com>
* AD7768_zed: Fix wideband filter bug
In SPI control mode, when not used as GPIO the FILTER pin and when a
crystal is used as the clock source, this pin must be set to 1.
The START pin must be tied to a logic 1 through a pull-up resistor, when
it is not used.
Use tcl script instead of static xmls for the interface.
Easier to maintain and are not gitignored.
Rename spi_master to spi_engine because every interface should be
prefixed by the IP name; in this case, spi_engine.
Also, remove interface/*.sv files on make clean and git ignore them.
Signed-off-by: Jorge Marques <jorge.marques@analog.com>
The extensions have been moved to docs tools.
The source code is available at
https://github.com/analogdevicesinc/doctools
And is installed as before:
(cd docs ; pip install -r requirements.txt --upgrade)
Since the package is listed on the requirements.txt file.
Also, add index for library and projects
Signed-off-by: Jorge Marques <jorge.marques@analog.com>
* Value 24 was wrongfully set for parameter LENGTH_WIDTH, because
it is not among the valid values, which are 28, 29, ..., 34. Set '28'
to be the default value
* Vivado Tcl somehow didn't accept the old expression set for
calculating the HBM_SEGMENTS_PER_MASTER parameter, so it was changed
accordingly to work. Dropped "expr", ".0" and "int ()" parsing and now
it works
Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
The introduction of sysid IPs on some Stratix 10 projects introduced a
problem where they would fail to build, due to mem_init_sys_file_path
not being defined. This is fixed now.
Signed-off-by: Laez Barbosa <laez.barbosa@analog.com>
* SPI Engine: fix early sdi data clear
In case an SPI read was immediately followed by a cs assert, the sdi
register was being cleared one cycle too soon, so that the data being
passed on was always 'b0.
Signed-off-by: Laez Barbosa <laez.barbosa@analog.com>
Previous level-based trigger could cause issues in some low
sampling rate setups. This commit changes it to edge-based.
Signed-off-by: Laez Barbosa <laez.barbosa@analog.com>
The lack of the create_xgui_files causes Vivado to exit with an error
when running multiple Vivado instances (parallel make case)
Signed-off-by: Jorge Marques <jorge.marques@analog.com>
Set validation ranges for DATA_WIDTH and NUM_OF_CS for the expected
min/max values in the verilog source code.
Also, fix swapped description for CPHA in the documentation.
Signed-off-by: Carlos Oliveira <caosjr8@gmail.com>
Jorge Marques
IstvanZsSzekely
ladace
Villyam
Stanca Pop
caosjr
PIoandan
Alin-Tudor Sferle
Sergiu Arpadi
LBFFilho
Iulia Moldovan
AndrDragomir
laurent-19
Jorge Marques
AndreiGrozav
caosjr