Commit Graph

4 Commits (a49eb5853b8b676e5724dc071abea9400ff48760)

Author SHA1 Message Date
Adrian Costina 39ac29bb01 AD9361: Altera, modified address width so that all registers are accessible
Modified qsys project with the new address span
2014-07-08 10:41:51 +03:00
Rejeesh Kutty b6052773b7 added adc/dac gpio registers 2014-06-27 14:45:58 -04:00
Rejeesh Kutty 10a7804e14 ad9361: altera wrapper updates 2014-06-25 15:26:06 -04:00
U-ANALOG\ACostina c73390b6c9 axi_ad9361: Intermediary check in for altera porting
This is work in progress. It will not work as it is
2014-04-11 17:40:34 +03:00