05c20af988
Merge pull request #430 from analogdevicesinc/update_tcl
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Rename projects for consistency
2020-02-06 16:32:40 +02:00
e00ee136f6
cn0506_mii Updates for Rev B board
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Because of the rmii mode requirements(external 50MHz clock) the
board will have the rx_err signal replaced on the FMC connector with the
50MHz external clock (D08/D20).
The rx_er will be shifted to the D9/D21 pins.
2020-02-03 11:20:18 +02:00
b3e475cb8b
ad_fmclidar1_ebz: Update the IO constraints to revB
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The IO location of the laser_driver_otw_n was moved from FMC_HPC_LA27_N
to FMC_HPC_LA31 (laser_gpio[12]).
laser_gpio[11:0] assignments were shifted with one bit to MSB, and laser_gpio[0]
got the old location of the laser_driver_otw_n.
2020-01-31 18:47:37 +02:00
135538b521
adi_project: Fixed kcu105 board file selection
2020-01-16 17:16:58 +02:00
db5e21cfb9
pluto revC: Add second RF channel
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-add second RF channel (without fir filters)
-use a more generic instantiation of the fir filters
-add util_cpack2 and util_upack2
2020-01-16 11:40:28 +02:00
f9c8ff26cf
pluto rev C hardware updates
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-connect axi_spi to board GPIOs
-connect axi IIC to board GPIOs
MIO49 SPI_CS (PS MIO49)
L10P SPI_MOSI (AXI_SPI)
L12N SPI_MISO (AXI_SPI)
L24N SPI_CLK (AXI_SPI)
L7N iic_sda (AXI_IIC)
L9N iic_scl (AXI_IIC)
2020-01-16 11:40:28 +02:00
e773b22087
adi_project: Updated board files version selection
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vivado will automatically select the latest version for a given board
2020-01-14 17:16:01 +02:00
fcf7bb035a
ad40xx: Fix data_width definition
2020-01-14 15:24:43 +02:00
d86fbb2a08
adi_board: fixed ddr memory mapping for microblaze projects
2020-01-13 12:25:23 +02:00
34ea5efdff
adi_project_xilinx: Use the latest board files
2020-01-13 12:25:23 +02:00
adfeb435a4
scripts: Update Vivado version to 2019.1
2020-01-13 12:25:23 +02:00
fa259c7975
ad40xx: Fix a typo
2020-01-10 10:20:06 +02:00
9497b1cace
ad40xx: Remove redundant upscaler IP, Add timing constraints
2020-01-09 11:32:31 +02:00
8db77d8f3a
ad_fmclidar1_ebz/README: Add Known Issues section
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Add description of the power-up issue and its solution.
2019-12-20 13:20:42 +02:00
d4b3a3f640
ad_fmclidar1_ebz/README: A10SOC rework guide
2019-12-18 14:47:00 +02:00
9ab4c0c783
dac_fmc_ebz: Passthrough GPIO signal for bypass
2019-12-06 11:04:45 +02:00
8b45d17eb9
dac_fmc_ebz: Only create dummy ports for unused
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lanes
2019-12-06 11:04:45 +02:00
09ad67bfd7
adrv9009zu11eg: Make the project more parametrizable
2019-12-04 14:59:18 +02:00
2e4ac278eb
ad_fmclidar1_ebz: Add documentation
2019-12-03 18:23:57 +02:00
3c83694755
adi_fir_filter_bd.tcl: Synchronize the control GPIO input to the core clock
2019-12-03 17:27:56 +02:00
82021edffe
adi_board.tcl:ad_xcvrcon: do not reorder common control
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When channels are not swapped in groups of four but are completely out of order
the common control channel can't be reordered based on the index of the
channel.
2019-11-30 12:29:32 +02:00
c2726ceac9
common:vcu118: move system memory to DDR C2
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The DDR controller for C2 for is much closer to the transceivers which
connect to the FMCp connector so designs does not have to span over all
three SLRs just over two reducing implementation and timing closure effort.
2019-11-28 16:17:44 +02:00
0cb5c0bdaf
adv9009zu11eg: Update FPGA to -2. Update DDR4 clock frequency
2019-11-27 16:27:44 +02:00
c44b4957b5
ad7134_fmc/zed: Fix IO definitions for SDI lines
2019-11-27 10:04:37 +02:00
88e80f604e
daq3:zcu102: fix GPIO double drive
2019-11-26 14:41:19 +02:00
8c39cf8560
scripts: adi_board.tcl: Update the axi_adxcvr to util_adxcvr connections
2019-11-26 12:57:53 +02:00
8131c86f75
m2k: Connect the adc_trigger reset
2019-11-25 13:14:18 +00:00
a06c74edc7
fmcjesdadc1: Change rx_div_clk to 125MHz
2019-11-20 10:50:18 +02:00
9260979b15
adrv9364: Added sysid to all projects
2019-11-20 10:43:54 +02:00
570dae7df6
adrv9361: Added sysid to all projects
2019-11-20 10:43:54 +02:00
dfe3258a4f
adrv9009zu11eg: Add axi_sysid
2019-11-19 10:29:57 +02:00
81d3a9eb66
adrv9009zu11eg: Reduce SPI Clock speed to meet timing
2019-11-19 10:29:57 +02:00
4b380fe640
ad7768-1evb: Add coraz7s support
2019-11-15 14:35:00 +02:00
40d839df5f
coraz7s: Initial commit
2019-11-15 14:35:00 +02:00
514aadb54e
m2k: Use dac trigger
2019-11-15 12:23:01 +00:00
a589a2c7eb
adrv9009_zu11eg_som: Change design partitioning
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Create a structure similar with ADRV936x projects
2019-11-14 15:25:23 +02:00
eab1e86544
adrv9364z7020: Rename *box project to *packrf
2019-10-29 16:07:08 +02:00
de324526e3
adrv9361z7035: Rename *box project to *packrf
2019-10-29 16:07:08 +02:00
fba7cac0c6
ad7768-1evb: Remove ADC2, update spi engine framework
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The second ADC was removed from the project, as the EV-AD7768-1FMCZ evaluation
board contains only one ADC. Therefore, all the IPs related to the
second ADC have been removed, too.
The data width supported by the spi IPs has been changed from 8 bits to
32 bits, therefore the axis_upscaler(util_axis_upscale_v1_0) and the
m_axis_samples_24(AXI4-Stream Data Width Converter) are no more necessary,
so they have been removed from the design.
The 24 bits width data transfer between the s_axis of axi_ad77681_dma
(AXI DMA Controller) and the offload_sdi of the spi_engine_offload is now made
directly.
2019-10-28 12:00:23 +02:00
4941d89fff
cn0506_mii: Add support on a10soc
2019-10-18 19:09:04 +03:00
fbb3a154ff
cn0506_mii: Add support on zcu102
2019-10-18 19:09:04 +03:00
3cb2392711
cn0506_mii: Add support on zc706
2019-10-18 19:09:04 +03:00
e98951d282
cn0506_mii: Add support on zed
2019-10-18 19:09:04 +03:00
8202c0025c
cn0506_mii: Common design initial commit
2019-10-18 19:09:04 +03:00
9323f4193c
m2k: Clean old interrupt connection style
2019-10-18 18:28:01 +03:00
a4547a32b6
pluto: Clean old interrupt connections style
2019-10-18 18:28:01 +03:00
fd4d32c408
projects/scripts/*xilinx*: Generate report utilization extra files
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Add commands to generate one extra file with resource utilization, in CSV format.
New commands executes only if ADI_GENERATE_UTILIZATION env variable is set.
2019-10-18 13:42:34 +03:00
5a4726b356
adrv9364z7020: Fix interrupt concatenation
2019-10-17 15:09:48 +03:00
f0f314f24b
adrv9361z7035: Fix interrupt concatenation
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None functional change, main goal is to increase consistancy in our
code base.
2019-10-17 15:09:48 +03:00
80333573c7
ad_fmclidar1_ebz/zcu102: Fix SYSREF input delay constraint
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Add one clock cycle input delay for the SYSREF input,
to compensate the high propegation delay of device_clk_BUFG.
2019-10-17 09:59:23 +03:00
StancaPop
AndreiGrozav
Istvan Csomortani
Sergiu Arpadi
Stanca Pop
István Csomortáni
Prasahnt Sivarajah
Adrian Costina
Laszlo Nagy
Stefan Raus