Adrian Costina
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09ad67bfd7
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adrv9009zu11eg: Make the project more parametrizable
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2019-12-04 14:59:18 +02:00 |
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Adrian Costina
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0cb5c0bdaf
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adv9009zu11eg: Update FPGA to -2. Update DDR4 clock frequency
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2019-11-27 16:27:44 +02:00 |
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Adrian Costina
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dfe3258a4f
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adrv9009zu11eg: Add axi_sysid
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2019-11-19 10:29:57 +02:00 |
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Adrian Costina
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81d3a9eb66
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adrv9009zu11eg: Reduce SPI Clock speed to meet timing
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2019-11-19 10:29:57 +02:00 |
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Adrian Costina
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a589a2c7eb
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adrv9009_zu11eg_som: Change design partitioning
Create a structure similar with ADRV936x projects
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2019-11-14 15:25:23 +02:00 |