Commit Graph

1598 Commits (a5b452cc27e07f47af20673ef64d88fc59103c3d)

Author SHA1 Message Date
Lars-Peter Clausen a5b452cc27 Add axi_generic_adc core
The axi_generic_adc core is a simple core that doesn't do much more then
implementing the AXI ADC register map and routing the enable and overflow
signals to the farbic.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-05-21 17:21:35 +02:00
Lars-Peter Clausen 033713ccb5 Add cordic demodulator module
The cordic_demod module takes in phase and data on s_axis interface then
performs a cordic demodulation and outputs the resulting I and Q component
data on the m_axis interface.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-05-21 17:21:35 +02:00
Lars-Peter Clausen cefbe3a0ff scripts/adi_ip.tcl: Add option to specify reset interface direction
Allow to specify the direction of the reset signal for a interface, this is
useful if the core itself generates the reset signal.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-05-21 17:21:35 +02:00
Lars-Peter Clausen 6b9906b22b Refresh Makefiles
Re-generate the Makefiles after a small update to the generation script:
- Entries are sorted alphabetically
- Empty dependency lines are skipped

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-05-21 14:21:54 +02:00
Adrian Costina ebbc0c6ed5 fmcomms5: zc706, removed debug related ila, as the pins were removed from the AD9361 IP 2015-05-21 14:19:22 +03:00
Adrian Costina 5ac7ebb8a3 axi_mc_*: Removed delay pins from up_adc_common 2015-05-21 14:03:58 +03:00
Istvan Csomortani a047d3990a fmcadc2_vc707: Fix interrupts
+ Remove some trailing whitespaces
+ Fix interrupt connections
2015-05-21 11:03:16 +03:00
Rejeesh Kutty 19b094cab5 daq2/a10gx- added jesd align 2015-05-20 15:39:27 -04:00
Rejeesh Kutty 465f7dff88 library/util_jesd_align -added 2015-05-20 15:38:43 -04:00
Rejeesh Kutty 9762c65868 library- jesd-align port name change 2015-05-20 14:25:21 -04:00
Rejeesh Kutty f1c30ac225 daq2/a10gx- qsys updates 2015-05-20 14:24:49 -04:00
Rejeesh Kutty 4927ca85c2 projects- jesd-align port name change 2015-05-20 14:24:26 -04:00
Rejeesh Kutty da0409b5a6 library- qsys components 2015-05-20 11:51:50 -04:00
Rejeesh Kutty 9b425736ac library: altera ip modifications 2015-05-20 10:41:21 -04:00
Rejeesh Kutty d48d3f4aa3 scripts/ip-alt- added 2015-05-20 09:11:18 -04:00
Rejeesh Kutty 52b6077a46 a10gx- 15.0 updates 2015-05-19 15:12:23 -04:00
Rejeesh Kutty e918588a4b library: remove axi-min-size parameter 2015-05-19 13:07:48 -04:00
Rejeesh Kutty 4fb1be0672 ad9680: delay changes 2015-05-19 12:53:56 -04:00
Rejeesh Kutty af7afd7366 ad9671: delay changes 2015-05-19 12:53:56 -04:00
Rejeesh Kutty 09a05fe9d8 ad9652: delay changes 2015-05-19 12:53:56 -04:00
Rejeesh Kutty 13156593f8 ad9643: delay changes 2015-05-19 12:53:56 -04:00
Rejeesh Kutty c8d3c04a05 ad9625: delay changes 2015-05-19 12:53:56 -04:00
Rejeesh Kutty f53204f9f9 ad9467: delay changes 2015-05-19 12:53:56 -04:00
Rejeesh Kutty 0805da3b6b fmcomms2/rfsom- enable dac delay 2015-05-18 16:45:54 -04:00
Rejeesh Kutty fe0ceb2530 delay-cntrl updates 2015-05-18 15:23:10 -04:00
Rejeesh Kutty 304a202d67 delay-cntrl updates 2015-05-18 14:57:05 -04:00
Rejeesh Kutty 2e257db109 delay-cntrl updates 2015-05-18 14:53:24 -04:00
Rejeesh Kutty 3e51d29f75 enable/txnrx- tdd changes 2015-05-18 14:28:20 -04:00
Rejeesh Kutty 0877c252ad delay-cntrl changes 2015-05-18 14:28:20 -04:00
Rejeesh Kutty 2bad47cf4f delay-cntrl: up-clk, direct access + tx 2015-05-18 14:28:20 -04:00
Rejeesh Kutty 6e047f78c6 delay-cntrl: up-clk, direct access + tx 2015-05-18 14:28:20 -04:00
Adrian Costina 2c1719095d util_axis_resize: Changed _ip.tcl format to the standard format 2015-05-18 17:25:07 +03:00
Adrian Costina c19749361d Makefiles: Updated makefiles to have as a result the programming file instead of the project file.
Also fixed altera projects dependencies
2015-05-18 17:22:46 +03:00
Rejeesh Kutty 672a5a4dfa a10gx- updates 2015-05-14 14:35:43 -04:00
Rejeesh Kutty b311b9dac6 a10gx- updates 2015-05-14 14:35:42 -04:00
Istvan Csomortani a07d11c3e9 axi_ad9361_tdd: Define control bits for continuous receive/transmit 2015-05-14 17:21:32 +03:00
Adrian Costina c9c05e21c2 axi_dmac: Updated constraints to cover cases when the hierarchy is rebuilt by synthesis 2015-05-13 16:34:06 +03:00
Istvan Csomortani 7c9bc40c75 axi_ad9361&TDD: Update TDD
+ Delete unnecessary registers
+ Add the module ad_addsub.v to resolve additions and subtractions inside TDD control
+ Redefine the burst logic
+ Redesign the control signal generations
+ Note: This patch fix the TDD related timing violations
2015-05-13 14:03:01 +03:00
Rejeesh Kutty a1d680ee6b ad9680- add hw tcl 2015-05-12 15:06:42 -04:00
Rejeesh Kutty 833a3de6b5 ad9680- add hw tcl 2015-05-12 15:06:39 -04:00
Rejeesh Kutty 48c769d431 ad9144- add hw tcl 2015-05-12 14:40:38 -04:00
Rejeesh Kutty 553f89f59d ad9144- add hw tcl 2015-05-12 14:39:57 -04:00
Rejeesh Kutty 3226ca4374 fmcadc4- ad9680 version 2015-05-11 13:55:02 -04:00
Rejeesh Kutty c28ff2ff9a fmcadc4- ad9680 version 2015-05-11 13:55:02 -04:00
Rejeesh Kutty 16541335e6 fmcadc4- ad9680 version 2015-05-11 13:55:02 -04:00
Rejeesh Kutty 2cd1d8a591 fmcadc4- ad9680 version 2015-05-11 13:55:02 -04:00
Rejeesh Kutty 0a6efaccca fmcadc4- ad9680 version 2015-05-11 13:55:02 -04:00
Rejeesh Kutty 848dac70d5 a10gx: updates-- 2015-05-11 11:56:27 -04:00
Rejeesh Kutty dc0eea5f0f a10gx: updates-- 2015-05-11 11:56:26 -04:00
Rejeesh Kutty bdc3f3d807 a10gx: updates-- 2015-05-11 11:56:24 -04:00