84b2ad51e2
license: Add some clarification to the header license
2017-05-31 18:18:56 +03:00
85ebd3ca01
license: Update license terms in hdl source files
...
Fix a few gramatical error, fix the path of the top level license
files.
2017-05-29 09:55:41 +03:00
10898d6618
constraints: Split the regmap CDC constraint into separate file
2017-05-25 15:12:16 +03:00
9055774795
all: Update license for all hdl source files
...
All the hdl (verilog and vhdl) source files were updated. If a file did not
have any license, it was added into it. Files, which were generated by
a tool (like Matlab) or were took over from other source (like opencores.org),
were unchanged.
New license looks as follows:
Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
Each core or library found in this collection may have its own licensing terms.
The user should keep this in in mind while exploring these cores.
Redistribution and use in source and binary forms,
with or without modification of this file, are permitted under the terms of either
(at the option of the user):
1. The GNU General Public License version 2 as published by the
Free Software Foundation, which can be found in the top level directory, or at:
https://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html
OR
2. An ADI specific BSD license as noted in the top level directory, or on-line at:
https://github.com/analogdevicesinc/hdl/blob/dev/LICENSE
2017-05-17 11:52:08 +03:00
c728299e71
altera- default to latest version
2017-05-12 13:25:17 -04:00
e4ae391237
axi adc cores: Add missing ports to up_adc_common instance
2017-05-12 13:39:05 +03:00
fea6eb68be
up_adc_common- port name changes
2017-05-10 14:45:17 -04:00
1c23cf4621
all: Update verilog files to verilog-2001
2017-04-13 11:59:55 +03:00
c1bdfca4c3
library: Delete all adi_ip_constraint process call
2017-04-06 12:36:47 +03:00
c46989e4e8
Makefile: Update Makefiles for libraries
2017-03-30 18:33:22 +03:00
873fbfd6d7
library: Update scripts with new constraints
...
Update all IPs tcl scripts with the new constraints files.
Refer to commit 335fef0
2017-03-30 16:16:02 +03:00
2419b3626b
ad9684- fix sdc typo
2017-03-23 12:49:44 -04:00
ae0f4672b2
daq1/a10gx- fix project to compile
2017-03-23 09:46:40 -04:00
8ebc8fe4e2
updated makefiles
2016-12-09 23:06:41 +02:00
7876c8ffa4
axi_ad9684: Add loaden and phase ports for altera support
2016-12-06 15:24:20 +02:00
a7d3df8757
axi_ad9684: Update hw tcl script for altera
2016-12-06 15:24:20 +02:00
de0c487195
axi_ad9684: Add Altera support for the core
2016-10-24 11:43:22 +03:00
91995c082d
axi_ad9684: Fixed up_drp_*data width
2016-10-12 13:20:26 +03:00
df485d7878
axi_ad9684: Fix the PN9 PRBS sequence monitor
2016-09-28 10:47:16 +03:00
ad16aec101
axi_ad9684: Fix SERDES modules
2016-09-26 11:14:35 +03:00
6837143110
library/ adc parameter changes
2016-09-23 13:44:47 -04:00
0cd608a7e2
lib_refactoring: Update Make files
2016-08-08 16:38:38 +03:00
df36902713
lib_refactoring: Fix path of the IO macros
2016-08-08 15:07:19 +03:00
d60bce654c
Makefiles: Updated Makefiles so they run correctly with gnuwin32 tools
2016-08-05 15:16:04 +03:00
6ebb32a194
library axi-slave missing protection signal added
2016-07-22 12:54:27 -04:00
c293c04634
hdl make updates
2016-06-01 13:53:09 -04:00
46eddd04be
library: port updates on mmcm
2016-03-22 12:50:59 -04:00
e1c5d6a8f7
axi_ad9684: Fix constraint file
2016-02-12 14:38:59 +02:00
4cc69c0cac
axi_ad9684: Add Makefile
2016-01-19 18:32:11 +02:00
c6cfd1a2b6
axi_ad9684: Initial check in
2016-01-19 11:13:45 +02:00
Istvan Csomortani
Rejeesh Kutty
AndreiGrozav
Istvan Csomortani
Adrian Costina
Shrutika Redkar