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687 Commits (a68463d033d4a0d69b91de02ae949f17c679ffe0)

Author SHA1 Message Date
Rejeesh Kutty a68463d033 rfsom: board updates 2015-03-10 15:26:31 -04:00
Rejeesh Kutty e38356b243 rfsom: board updates 2015-03-10 15:26:24 -04:00
Rejeesh Kutty c0eef42647 adi_board: enable ps7 hp if needed 2015-03-09 16:12:23 -04:00
Rejeesh Kutty 59457cb3d4 daq2/zc706: base system updates 2015-03-09 16:10:56 -04:00
Rejeesh Kutty ce5ece5494 daq2/zc706: base system updates 2015-03-09 16:09:54 -04:00
Rejeesh Kutty 104782af87 daq2/kcu105: base system updates 2015-03-09 16:09:07 -04:00
Rejeesh Kutty 548ae9d39e daq2: move gpio/spi to base design 2015-03-09 16:08:25 -04:00
Rejeesh Kutty f0395b646c plddr3: ad_connect updates 2015-03-09 16:07:37 -04:00
Rejeesh Kutty 031dffa80c zc706: move gpio/spi to base design 2015-03-09 16:07:02 -04:00
Rejeesh Kutty 2302f282d3 sys_dmafifo: ad_connect updates 2015-03-09 16:06:06 -04:00
Rejeesh Kutty 545c0baada kcu105: gpio led/sw merged to bd default 2015-03-09 16:05:28 -04:00
Rejeesh Kutty b31d9abd91 kcu105: gpio/spi moved to base design 2015-03-09 16:04:09 -04:00
Rejeesh Kutty ed28b47203 board: optimize interconnect for performance 2015-03-06 12:38:52 -05:00
Rejeesh Kutty d5eaadd872 daq2: remove ila for kcu105 ddr-300M timing 2015-03-06 12:38:08 -05:00
Rejeesh Kutty 1db5f4696f kcu105: isolate ddr-300M from interconnect-100M timing 2015-03-06 12:37:31 -05:00
Rejeesh Kutty da5b136f5a daq2+base: board tcl updates 2015-03-05 10:56:36 -05:00
Rejeesh Kutty 0ac1676318 daq2+base: board tcl updates 2015-03-05 10:56:36 -05:00
Rejeesh Kutty 7fba7cc6e5 daq2+base: board tcl updates 2015-03-05 10:56:36 -05:00
Rejeesh Kutty af465cbc80 daq2+base: board tcl updates 2015-03-05 10:56:36 -05:00
Rejeesh Kutty 1220b53c8c daq2+base: board tcl updates 2015-03-05 10:56:36 -05:00
Rejeesh Kutty 75c4228987 daq2+base: board tcl updates 2015-03-05 10:56:36 -05:00
Rejeesh Kutty 605d23d3a4 daq2+base: board tcl updates 2015-03-05 10:56:36 -05:00
Rejeesh Kutty 91765fdd82 daq2+base: board tcl updates 2015-03-05 10:56:36 -05:00
Rejeesh Kutty 7bf4141a3f daq2+base: board tcl updates 2015-03-05 10:56:36 -05:00
Rejeesh Kutty bf1388b05e kcu105: rev.d changes 2015-03-04 12:43:04 -05:00
Rejeesh Kutty 4f918cdce9 2014.4.1 ultrascale updates 2015-02-26 16:10:57 -05:00
Rejeesh Kutty 847c2e049a kcu105: removed lutram constraints 2015-02-26 16:09:55 -05:00
Istvan Csomortani 1613f7fb41 cftl_cip: Add util_pmod_fmeter IP to library 
Frequency meter IP for CN0332.
 2015-02-23 17:20:12 +02:00
Lars-Peter Clausen abde4048e0 fmcomms1: Add extra AXI slice on ADC DMA path 
Add a extra AXI slice on the ADC DMA data path to the HP interconnect to
improve the timing.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
 2015-02-20 16:43:45 +01:00
Rejeesh Kutty b9d16a7eb1 scripts: renaming board parameters 2015-02-20 09:12:30 -05:00
Rejeesh Kutty 288f5378ff rfsom: schematic changes 2015-02-18 14:32:41 -05:00
Rejeesh Kutty 93e2bcd911 rfsom: schematic changes 2015-02-18 14:32:30 -05:00
Rejeesh Kutty 383cf3b3a3 rfsom: schematic changes 2015-02-18 14:32:20 -05:00
Rejeesh Kutty d2e9b1fe03 rfsom: schematic changes 2015-02-18 14:32:04 -05:00
Istvan Csomortani 3113abf038 cftl_cip: Add gpio counter for CN0332 
Add a counter core to the design, to support the CN0332 pmod with a speed sensor.
Change a naming for the custom cores.
 2015-02-18 18:24:46 +02:00
Rejeesh Kutty e111e1336e conflicts- 2015-02-06 22:14:21 -05:00
Istvan Csomortani 2d607d765b cftl_cip: Add a clock input to the device core, for the SPI clock. 
This clock can be adjustable from the system_project.tcl
 2015-02-04 14:55:17 +02:00
Rejeesh Kutty 996e1b7970 rfsom: constraint updates 2015-02-03 14:20:34 -05:00
Adrian Costina fd2ab02174 cftl_std: Added in the constraint file comments regarding supported CFTLs 2015-01-29 16:27:43 +02:00
Istvan Csomortani d69d105b5d vc707_common: Fix address mapping 
The axi_ethernet/eth_buf/S_AXI_2TEMAC address space and axi_ethernet/eth_mac/s_axi/Reg address
segment does not exist in 2014.4.
 2015-01-29 12:22:06 +02:00
Istvan Csomortani e8ff30119d vc707_xdc: Delete unnecessary clock definition 2015-01-29 11:39:10 +02:00
Istvan Csomortani 6c8ea24f20 common: Update VC707 base design to 2014.4 2015-01-28 16:24:52 +02:00
Istvan Csomortani e1d8dd10a9 daq2: Initial check in of the VC707 based project 
NOTE: Can not communicate with the clock chip, rx/tx PLL not locking.
 2015-01-28 16:24:06 +02:00
Istvan Csomortani 659e0cca4e cftl_cip: Initial check in. 
Project cftl_cip supports the following Circuits from the Lab pmods:
 + EVAL-CN0350-PMDZ
 + EVAL-CN0335-PMDZ
 + EVAL-CN0336-PMDZ
 + EVAL-CN0337-PMDZ
Note: Additional testing needed!
 2015-01-23 18:29:32 +02:00
Adrian Costina 463a3bbc88 cftl_std: Updated project. Switched to PS7 gpio. Renamed signals. 2015-01-23 14:11:33 +02:00
Adrian Costina 9672271155 fmcjestadc1: a5gt: Updated project to work with linux and fixed ethernet 
- added phy reset mechanism for proper functioning of the ethernet
- not all DDR is accesible, as NIOS2 can't access it with MMU enabled
 2015-01-23 13:30:56 +02:00
Adrian Costina 5a77ab0161 a5gt:common: Added phy reset signal from ethernet in pin assignments 2015-01-23 12:31:41 +02:00
Adrian Costina 050f17e034 a5gt3: common: corrected naming in pin assignments. added reset signal from FPGA2 2015-01-23 12:30:16 +02:00
Rejeesh Kutty 72e89852b6 daq2/kc705: 2014.4 updates 2015-01-14 12:58:08 -05:00
Rejeesh Kutty 024d9e7309 replace export hardware -- hwdef/sysdef 2015-01-13 13:40:21 -05:00