pluto_hdl_adi

Commit Graph

Author	SHA1	Message	Date
Istvan Csomortani	363494ab9c	library/scripts: Rename adi_ip.tcl to adi_ip_xilinx.tcl	2019-06-29 06:53:51 +03:00
Istvan Csomortani	0e7b38ebcf	axi_pulse_gen: Initial commit The axi_pulse_gen is a generic PWM generator, which can be configured through an AXI Memory Mapped interface. The current register map look like follows: 0x00 - VERSION 0x04 - ID 0x08 - SCRATCH 0x0C - IDENTIFICATION - 0x504c5347 which stands for 'PLSG' in ASCII 0x10 - CONFIGURATION - contains reset and load bits 0x14 - PULSE_PERIOD 0x18 - PULSE_WIDTH Also update all the other modules, which instantiate the util_pulse_gen.	2019-03-20 08:21:22 +00:00

Author

SHA1

Message

Date

Istvan Csomortani

363494ab9c

library/scripts: Rename adi_ip.tcl to adi_ip_xilinx.tcl

2019-06-29 06:53:51 +03:00

Istvan Csomortani

0e7b38ebcf

axi_pulse_gen: Initial commit

The axi_pulse_gen is a generic PWM generator, which can be configured
through an AXI Memory Mapped interface.

The current register map look like follows:

  0x00 - VERSION
  0x04 - ID
  0x08 - SCRATCH
  0x0C - IDENTIFICATION - 0x504c5347 which stands for 'PLSG' in ASCII
  0x10 - CONFIGURATION - contains reset and load bits
  0x14 - PULSE_PERIOD
  0x18 - PULSE_WIDTH

Also update all the other modules, which instantiate the util_pulse_gen.

2019-03-20 08:21:22 +00:00

2 Commits (a6cff0f804a7ce6e4495b52441fc415fa500803e)