zcy
/
pluto_hdl_adi
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity
5,165 Commits
1 Branch
0 Tags
23 MiB
Commit Graph

2756 Commits (a6cff0f804a7ce6e4495b52441fc415fa500803e)

Author SHA1 Message Date
Adrian Costina a6cff0f804 motcon2_fmc: Remove project 2019-07-22 13:23:43 +01:00
Istvan Csomortani 6a721c0bf0 adi_env: Update system level environment variable definition 
Our internal repository was changed from phdl to ghdl. Update the
adi_env.tcl scripts and other scripts, which depends on the $ad_ghdl_dir
variable. This way the tools will see all the internal IPs too.
 2019-07-22 11:00:45 +03:00
AndreiGrozav ce5aadb3e4 adrv9361z7035/common/ccbox_constr.xdc: Cosmetics only 2019-07-17 10:37:30 +03:00
AndreiGrozav 6f627c2105 adrv9361z7035/ccbox: Keep by default in powerdown the 12V PS 
Because of build hazards, the power supply can be randomly powered on,
when the pin is left in high impedance.
 2019-07-17 10:37:30 +03:00
AndreiGrozav 5f1cb18c9b ad7616_sdz/zc706: Fix Build 
- Fix typo
- Remove the unused(old flow) ps interupts
 2019-07-10 12:51:42 +03:00
Istvan Csomortani e1d9a36ae0 scripts/adi_project_intel: Rename ALT_NIOS_MMU_ENABLED to NIOS_MMU_ENABLED 2019-06-29 06:53:51 +03:00
Istvan Csomortani 04ce10a570 cosmetics: Change Altera to Intel in comments 2019-06-29 06:53:51 +03:00
Istvan Csomortani b0fbe1bb57 util_clkdiv: Seperate the IP source into an intel and xilinx version 2019-06-29 06:53:51 +03:00
Istvan Csomortani 5329458a62 library/scripts: Rename adi_ip_alt.tcl to adi_ip_intel.tcl 2019-06-29 06:53:51 +03:00
Istvan Csomortani 363494ab9c library/scripts: Rename adi_ip.tcl to adi_ip_xilinx.tcl 2019-06-29 06:53:51 +03:00
Istvan Csomortani 6e6f1347d7 project/scripts: Rename adi_project_alt.tcl to adi_project_intel.tcl 2019-06-29 06:53:51 +03:00
Istvan Csomortani a589753d92 project/scripts: Rename adi_project.tcl to adi_project_xilinx.tcl 2019-06-29 06:53:51 +03:00
Istvan Csomortani 43725429ac adi_project: Rename the process adi_project_xilinx to adi_project 2019-06-29 06:53:51 +03:00
Istvan Csomortani ec67a381e4 adi_project: Rename the process adi_project_altera to adi_project 2019-06-29 06:53:51 +03:00
Istvan Csomortani 79b6ba29ce all: Rename altera to intel 2019-06-29 06:53:51 +03:00
Sergiu Arpadi ba4a915af0 ad40xx/zed: fixed system_bd 
spi_engine_execution: fixed sdo default
 2019-06-28 11:18:29 +03:00
Istvan Csomortani cf9d0814d5 ad40xx/zed: Place all the SPI registers near IOB 2019-06-28 11:18:29 +03:00
Istvan Csomortani 10e1abc22f ad40xx_fmc/zed: Delete IOB TRUE constraints 
Vivado can not apply the IOB TRUE constraint to only one bit of a
registers. So these constraints will generate several CRITICAL WARNING.

Taking into consideration the maximum used frequencies and current
architecture these constraints are not critical.
 2019-06-28 11:18:29 +03:00
Laszlo Nagy 6b110b6fb8 ad5758_sdz/zed: system constraint file cleanup 
removed redundant PACKAGE_PIN properties
 2019-06-28 11:18:29 +03:00
Laszlo Nagy 0f2a1e7602 ad5758_sdz: Initial commit 
Initial version of AD5758 SDZ evaluation board support on ZedBoard.
No critical warnings in the Vivado log.
Bitstream generation passing.
Bring-up on actual board not done.
 2019-06-28 11:18:29 +03:00
Istvan Csomortani 9ab88f1200 ad40xx: Initial commit 2019-06-28 11:18:29 +03:00
Istvan Csomortani b46a28d42f adum7701: Delete redundant interrupt port in system_top 2019-06-28 11:18:29 +03:00
Istvan Csomortani 6668accc96 ad7405 : Initial commit 
This project is an inital version of the ADuM7701 (CMOS) or AD7405 (LVDS)
reference board.
 2019-06-28 11:18:29 +03:00
Istvan Csomortani 554feaa1af util_pulse_gen: Update ports for all outdated instance 
The new version of util_pulse_gen has different ports and port names.

Update all the instance:
  - AD738x_FMC
  - AD7768EVB
  - ADAQ7980_SDZ
 2019-06-28 11:18:29 +03:00
Istvan Csomortani 7fa620d253 gtm_projects: Update system_top 
In the latest system_top file we are not bringing out all the interrupt
signals from the block design. Delete all interrupt ports from the
system_wrapper instance.

Following projects were changed:

  - AD5766_SDZ
  - AD7134_FMC
  - AD7616_SDZ
  - AD77681EVB
  - AD7768EVB
  - ADAQ7980
 2019-06-28 11:18:29 +03:00
Istvan Csomortani 21ce53f765 Revert "Move GTM projects to gtm_projects branch" 
This reverts commit 171093eca4.
 2019-06-28 11:18:29 +03:00
Istvan Csomortani f22f448d4b daq3:vcu118: Delete constraint related to smart connect 
Apparently this constraint will cause more harm than good. The tool will
try to prevent an invalid hold violation by increasing the net delay,
causing a setup violation on the same path. (inside the smart connect)

See more info here:
https://forums.xilinx.com/t5/AXI-Infrastructure/Smartconnect-and-Synchronous-Clock-Domain-Crossing-Issues/td-p/904824
 2019-06-27 13:47:24 +03:00
Istvan Csomortani 4896a84c2d ad9739a_fmc: DMA should use $sys_dma_resetn 2019-06-21 09:54:21 +03:00
Istvan Csomortani e0a010c959 ad9625_fmc: DMA should use $sys_dma_resetn 2019-06-21 09:54:21 +03:00
AndreiGrozav 4812f64cdc ad9434: Fix axi_ad9434_dma timing closure 
axi_ad9434_dma/m_dest_axi_aresetn should use sys_dma_resetn
 2019-06-21 09:54:21 +03:00
AndreiGrozav 0a3a99bf83 m2k: Define SPI clock constraint 2019-06-21 09:53:14 +03:00
Sergiu Arpadi 0bbe501764 adrv9009_zu11eg_som: added axi_fan_control 2019-06-14 17:08:38 +03:00
Sergiu Arpadi c159909823 adrv9009_zu11eg_som: added i2s 2019-06-14 17:08:38 +03:00
Adrian Costina 9409df6a6f adrv9009_zu11eg: Initial commit 
Observation and RX should never run at the same time.
Given that there is no FIFO on the RX and OBS paths, they will use the higheste performance HP ports, which are HP1 and HP2
 2019-06-14 17:08:38 +03:00
Istvan Csomortani 95afc461a6 fmcomms5: DMA should use $sys_dma_resetn 2019-06-13 10:59:43 +03:00
Istvan Csomortani 2e05b70d94 fmcomms11: DMA should use $sys_dma_resetn 2019-06-13 10:59:43 +03:00
Istvan Csomortani dafc97f43a fmcjesdadc1: DMA should use $sys_dma_resetn 2019-06-13 10:59:43 +03:00
Istvan Csomortani 424abe0c02 adrv9009: DMA should use $sys_dma_resetn 2019-06-13 10:59:43 +03:00
Istvan Csomortani 5266d2ae88 ad6676evb: DMA should use $sys_dma_resetn 2019-06-13 10:59:43 +03:00
Istvan Csomortani 44a9331471 fmcomms2:fmcomms5: ZCU102 uses 500MHz IO delay clock 2019-06-11 18:13:06 +03:00
Istvan Csomortani 993497438b adi_project:adi_project_run: Check if $num_reg exist 2019-06-11 18:13:06 +03:00
Istvan Csomortani 896ea4925d adi_board: Fix ad_mem_hpx_interconnect proc 
Make the lsearch command more robust.
 2019-06-11 18:13:06 +03:00
Istvan Csomortani 019390f9bf block_design: Updates with new reset net variables 2019-06-11 18:13:06 +03:00
Istvan Csomortani 0e750bea42 adrv9009: Fix dma_clk tree 2019-06-11 18:13:06 +03:00
Istvan Csomortani 9072779e41 adrv9371x: Clean out system_db.tcl 2019-06-11 18:13:06 +03:00
Istvan Csomortani de510b45ab base: Add system_processor_rst for all the global clocks 2019-06-11 18:13:06 +03:00
Istvan Csomortani 7960b00684 block_design: Update with new clock net variables 
Using the new clock net variables in all Xilinx block designs.
 2019-06-11 18:13:06 +03:00
Istvan Csomortani 20c714eccf common: Define three global clock nets 
For all the Xilinx base design, define three global clock nets, which
are saved in the following three global variable: $sys_cpu_clk, $sys_dma_clk
and $sys_iodelay_clk.

These clock nets are connected to different clock sources depending of
the FPGA architecture used on the carrier. In general the following
frequencies are used:

  - sys_cpu_clk     - 100MHz
  - sys_dma_clk     - 200MHz or 250Mhz
  - sys_iodelay_clk - 200MHz or 500Mhz
 2019-06-11 18:13:06 +03:00
Istvan Csomortani 48d2c9d36f axi_ad9361: Define a MIMO enabled parameter 
Define a MIMO_ENABLE parameter for the core, which will insert
and additional de-skew logic to prevent timing issues coming from
the clock skew differences of two or multiple AD9361.
 2019-06-10 15:16:47 +03:00
Istvan Csomortani a4a9d0a19d fmcomms11/zc706: Relax core clock timing to 250MHz/125MHz 2019-06-10 11:23:41 +03:00