7befef6662
fmcomms2_zed: Update design to the new hdl framework
2015-03-13 18:52:57 +02:00
ea303c6f61
zc702: Updated base design to the latest model
2015-03-13 12:44:08 +02:00
8ad8ec4d1e
ml605 removed
2015-03-12 13:00:28 -04:00
68361bafd4
zc706_base: The FCLK_CLK2 is not used.
2015-03-11 18:10:32 +02:00
ae16aeb064
kcu105/adv7511: moved hdmi/spdif out of base design
2015-03-10 16:15:15 -04:00
d7993401e6
kcu105/adv7511: moved hdmi/spdif out of base design
2015-03-10 16:15:14 -04:00
8967903d76
zc706: intr sensitivity level-high
2015-03-10 16:05:05 -04:00
a68463d033
rfsom: board updates
2015-03-10 15:26:31 -04:00
e38356b243
rfsom: board updates
2015-03-10 15:26:24 -04:00
f0395b646c
plddr3: ad_connect updates
2015-03-09 16:07:37 -04:00
031dffa80c
zc706: move gpio/spi to base design
2015-03-09 16:07:02 -04:00
2302f282d3
sys_dmafifo: ad_connect updates
2015-03-09 16:06:06 -04:00
545c0baada
kcu105: gpio led/sw merged to bd default
2015-03-09 16:05:28 -04:00
b31d9abd91
kcu105: gpio/spi moved to base design
2015-03-09 16:04:09 -04:00
1db5f4696f
kcu105: isolate ddr-300M from interconnect-100M timing
2015-03-06 12:37:31 -05:00
91765fdd82
daq2+base: board tcl updates
2015-03-05 10:56:36 -05:00
7bf4141a3f
daq2+base: board tcl updates
2015-03-05 10:56:36 -05:00
bf1388b05e
kcu105: rev.d changes
2015-03-04 12:43:04 -05:00
383cf3b3a3
rfsom: schematic changes
2015-02-18 14:32:20 -05:00
d2e9b1fe03
rfsom: schematic changes
2015-02-18 14:32:04 -05:00
996e1b7970
rfsom: constraint updates
2015-02-03 14:20:34 -05:00
d69d105b5d
vc707_common: Fix address mapping
...
The axi_ethernet/eth_buf/S_AXI_2TEMAC address space and axi_ethernet/eth_mac/s_axi/Reg address
segment does not exist in 2014.4.
2015-01-29 12:22:06 +02:00
e8ff30119d
vc707_xdc: Delete unnecessary clock definition
2015-01-29 11:39:10 +02:00
6c8ea24f20
common: Update VC707 base design to 2014.4
2015-01-28 16:24:52 +02:00
5a77ab0161
a5gt:common: Added phy reset signal from ethernet in pin assignments
2015-01-23 12:31:41 +02:00
050f17e034
a5gt3: common: corrected naming in pin assignments. added reset signal from FPGA2
2015-01-23 12:30:16 +02:00
72e89852b6
daq2/kc705: 2014.4 updates
2015-01-14 12:58:08 -05:00
b595cce697
kcu105-daq2-2014.4-- intermediate fixes
2015-01-13 13:40:18 -05:00
b0b4bfe531
kcu105-daq2-2014.4-- intermediate fixes
2015-01-13 13:40:17 -05:00
47871287f3
kc705: Updated base project with linear flash. Updated all depending projects
2015-01-13 10:19:07 +02:00
65d9f08763
zc706: mig 2014.4
2015-01-09 14:12:52 -05:00
868df1aac8
zc706: mig 2014.4
2015-01-09 14:12:51 -05:00
f566268db5
zed_common: Updated common to 2014.4
2015-01-08 11:59:26 +02:00
eb569b991d
dmafifo- remove util fifo setup
2015-01-06 16:23:14 -05:00
9e707d8a33
rfifo: wrapper updates
2015-01-06 16:17:33 -05:00
a944deebd5
wfifo: wrapper updates
2015-01-06 16:17:25 -05:00
61ba4f4357
rfsom: updated to rfsom
2014-12-23 14:03:58 -05:00
614dfcd93c
rfsom: updated to rfsom
2014-12-23 14:03:57 -05:00
ee52602c89
rfsom: initial commit
2014-12-23 14:03:55 -05:00
0de1a38245
zc706: 2014.4 update
2014-12-23 14:03:52 -05:00
71baa129a7
VC707: Fixed linear flash timings
2014-12-19 15:45:14 +02:00
59e610be09
zc706_constr: Move the sys_rst related constraint definition to zc706_system_mig_constr.xdc
2014-12-17 19:07:43 +02:00
77fa96fa67
plddr3: sys-rst from board pushbutton
2014-12-15 12:58:54 -05:00
ed7f8b4908
plddr3: sys-rst from board pushbutton
2014-12-15 12:58:44 -05:00
caa0268434
base_design: External IIC reset is connected to Vcc
...
External IIC reset is connected to Vcc in case of AC701, KC705 and VC707
2014-12-11 11:13:07 +02:00
e7c920bbd9
fmcomms2/ml605: compilation fixes
2014-12-09 14:32:39 -05:00
a6b7b9d880
ad9467_kc705: Fix memory segment offset for SEG_axi_ddr_cntrl
2014-12-09 16:20:39 +02:00
7e18162632
projects/common/kcu105/kcu105_system_bd: Restore axi_ethernet SupportLevel 0
...
Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
2014-12-05 14:48:37 +01:00
34ffa15b12
zynq_plddr3: Fix PLDDR3's Reset Generator
...
Reset generator's external reset signal was active low, but the GT reset is active high, and both the DDR controller and FIFO2S were in reset.
Therefore the external reset active state is changed to active high. This setup in general is made by the tool automatically, in order to do it correctly, need to
set this two property of the reset generator.
2014-12-04 15:39:17 +02:00
3cc890e604
projects/common: KCU105 VC707 update and sync axi_ethernet:6.1 features
...
Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
2014-12-04 09:49:09 +01:00
3bc9b25e96
projects/common: KCU105 VC707 KC705 sync microblaze core defaults
...
Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
2014-12-04 09:47:02 +01:00
12f1873e17
kc705_base: Define sys_addr_mem_seg for dmafifo
2014-11-26 15:08:55 +02:00
c0f4d7e2b5
mitx045_common: Definition file patch
...
In 2014.2 tool version, the way how a definition file needs to be applied is different
The command "apply_bd_automation" should be used, instead setting property PCW_IMPORT_BOARD_PRESET
In non-project mode (PR design flow), after creating the static design the type of the board is set.
NOTE: the definition file for mitx must be installed accordingly in order to get this work
See link: http://zedboard.org/support/documentation/2056
2014-11-21 19:14:37 +02:00
cdd1408d3c
dmafifo: parameterized address width
2014-11-20 09:28:02 -05:00
e3378cd6cb
mitx045_board_definition: revert old board definition file
...
Revert commit 4f6aa159b8
2014-11-18 10:05:55 +02:00
5baa015246
kc705_base: Delete timing constraints
2014-11-13 16:30:37 +02:00
074662a622
dmafifo: common interface with fifo2s
2014-11-12 15:24:31 -05:00
c6af2696b3
plddr3: internal buswidth/clock conversion
2014-11-12 14:43:48 -05:00
05ed98f884
common: Updated common constratins for ac701, kc705, vc707, zc702
2014-11-11 12:35:44 +02:00
2d9a529ab8
kcu105: ddr - 800M
2014-11-06 16:50:37 -05:00
4634a4f868
vc707: Added linear flash to the base design
2014-11-05 17:18:40 +02:00
4f815b99a1
kc705_base: Fix sys_concat_intc input connections
...
All the unused input pins need to be connected to ground.
2014-11-03 13:02:08 +02:00
f7588131da
ac701_base: Interrupt update
2014-11-03 13:02:04 +02:00
b92636c6eb
kc705_base: Interrupt update
2014-11-03 13:02:03 +02:00
16cdae3001
mitx045_base: Delete unnecessary timing constraints.
2014-10-31 11:50:49 +02:00
67bec719f7
mitx045_base: Interrupt update
2014-10-31 11:45:33 +02:00
56859ad4c9
sys_dmafifo: use internal memory
2014-10-30 15:26:28 -04:00
7ae003cf82
zed_base: Interrupt update
2014-10-30 19:00:05 +02:00
ba53e156e3
ZC702_base: Interrupt update
2014-10-30 18:39:49 +02:00
f595b86576
kcu105: lutram constraints for ies
2014-10-30 11:20:27 -04:00
4c0e4d280f
dmafifo: internal version- light duty
2014-10-30 11:12:13 -04:00
360e7104b6
dmafifo: axi version- heavy duty
2014-10-30 11:12:12 -04:00
2e01ad2eec
ad9625_fmc/zc706: ps7 interrupt updates
2014-10-29 12:13:44 -04:00
f83622a2e6
daq2/kcu105: interrupt updates
2014-10-28 15:51:42 -04:00
4788d09620
vc707: interrupt updates
2014-10-28 15:42:55 -04:00
a870603db5
common_bd: Update the common block designs to the new IRQ path
...
Avoid the use of xil_concat module by using the ad_interrupts.
2014-10-27 19:44:25 +02:00
d1e3993bd0
kcu105: daq2 updates
2014-10-27 09:59:56 -04:00
d471b61f3e
fifo: merge zynq and non-zynq
2014-10-27 09:59:54 -04:00
10b898a62d
zed_base: Fix IRQ layout.
...
Just a temporally fix of IRQ layout.
2014-10-27 14:46:26 +02:00
43cdafe1e2
kcu105: iic-rstn removed
2014-10-22 16:33:52 -04:00
dcdba475f7
vc707_common: Fix net name sys_100m_resetn
2014-10-22 15:41:36 +03:00
767179dce9
adv7511_zc706: Fix IRQ layout
...
Fix IRQ connection, this layout works on Linux
2014-10-21 17:44:28 +03:00
5deffd57b1
zed: Remove top level constraints
...
Remove top level constraints from the ZED base design.
2014-10-20 13:20:27 +03:00
14ccdaaa78
kcu105: removed spdif reset
2014-10-17 14:00:00 -04:00
e73b3b52dc
kcu105: ethernet fix
2014-10-17 13:47:50 -04:00
6d76e0b768
zc706: remove top level constraints
2014-10-15 14:51:02 -04:00
5715c5b28f
dmafifo: axi stream interface
2014-10-15 14:50:57 -04:00
7d3be14ab5
common: Connect audio clkgen reset
...
While we are at it also hide the unused locked pin.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-10-15 18:44:46 +03:00
fd89458708
common: Set cpu interconnect strategy to minimize area
...
There will rarely be concurrent access to the peripheral control bus
interconnect, so there is no need to optimize for performace. Setting the
interconnect strategy to minimize area can reduce the resource usage by
~90%.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-10-15 18:43:54 +03:00
d2a04856a9
common: Fix xlconstant output pin name
...
On 2014.2 xlconstant output pin name is 'dout'.
2014-10-15 15:37:06 +03:00
43e9b0c7a6
common: Disable TTC0 MMIO routing for PS7
...
We do not use the ttc0 to MMIO routing, but it is enabled by default, so
explicitly disable it.
2014-10-10 16:19:51 +03:00
4f6aa159b8
mitx045: Base design now support 2014.2
2014-10-09 15:11:28 +03:00
cd42345324
projects/common/xxx/xxx_system_bd.tcl: 'Update microblaze defaults
...
Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
2014-10-07 09:17:24 +02:00
f0927afd0b
ad9625_fmc: add dma fifo for non-zynq
2014-10-01 14:51:14 -04:00
041d8faaf7
common: Updated common projects for ac701/kc702/zc702/zed to vivado 2014.2
2014-09-30 10:31:00 +03:00
7c98a783c5
2014.2 updates
2014-09-23 12:32:33 -04:00
dd7bac41c1
daq1 : Update project to 2014.2
...
- Cores are upadted
- Concat module does not swap output anymore
- Clock signal name ps7_clk_* changed to clk_fpga_*
2014-09-22 17:33:50 +03:00
fb5d212370
daq2/kcu105: fixed timing violations
2014-09-19 15:55:42 -04:00
a3dbd5ac00
projects/common/vc707/vc707_system_bd: AD9625_FMC update to 2014.2
...
Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
2014-09-16 14:59:36 +02:00
41cc92ef49
Remove BASEADDR/HIGHADDR parameters
...
This is unused and unneeded. The AXI interconnect will make sure that a
peripheral only gets requests that are meant for it, there is no need to
check the address in the peripheral itself.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-09-11 12:26:37 +02:00
647a26e19c
projects/common/vc707/vc707_system_bd.tcl: Select Linux MMU settings
2014-09-10 17:40:36 +02:00
50faf0c53a
Remove executable flags from non-exectuable files
2014-09-09 15:05:06 +02:00
b58e425b44
daq2/kcu105: timing improvement -register slices hang
2014-09-08 10:24:56 -04:00
72f31370ef
a5gt: ethernet-fpga lvds mode
2014-09-04 11:19:25 -04:00
3deb55bb98
a5gt: ethernet i/o changed to lvds
2014-09-04 11:19:24 -04:00
5a42c10233
projects/fmcomms2/c5soc: Added video output. HPS SPI was replaced by 3 Wire SPI.
2014-08-27 21:46:23 +03:00
7b280b3bbf
fmcomms6: zc706 build-only version
2014-08-27 10:44:37 -04:00
a49eb5853b
ZED, ZC702: Added contraints so that projects can successfully synthesize on linux systems
...
For ZC706 Fixed one constraint which was not correct
2014-08-26 16:28:41 +03:00
cb29b83b05
a5gt: updates to match a5gt
2014-08-25 10:46:59 -04:00
b481df0b5f
library: local constraints async groups
2014-08-14 15:09:51 -04:00
39bb7ca231
a5soc: fmcjesdadc1+hdmi version
2014-08-14 09:05:38 -04:00
96969079ce
a5soc: fixes for 14.0 and spi conflicts
2014-08-11 16:46:37 -04:00
6c6cab0e16
fmcomms2: ZC706 modified constraints for linux build machines
...
The added constraints allow the project to successfully pass timing on some ubuntu or debian build machines.
2014-08-01 17:34:36 +03:00
663588eeaf
daq2/kcu105: working ddr version
2014-07-29 09:15:30 -04:00
db2386a351
daq2/kcu105: latest mig updates
2014-07-23 16:25:55 -04:00
db1c931736
ad9625_plddr: PL DDR3 fixes
...
- Modified the axi slave interface handler
- Increased the rfifo_mem input depth to prevent overflow
2014-07-23 19:34:44 +03:00
2b6ce1e504
zc706_plddr3 : Fix axi_fifo2s_axi_mrst net
2014-07-21 15:10:36 +03:00
2955b9db78
fifo2s: flush if no request, c5soc: 14.0
2014-07-15 16:25:33 -04:00
b434fe6dd5
fmcomms5: register map changes
2014-07-08 16:57:43 -04:00
c75e6b3043
kcu105 pwr-good removed
2014-07-07 09:56:13 -04:00
a388ccab0a
fmcomms2/c5soc: initial checkin
2014-07-02 14:56:00 -04:00
c1b7fc17f5
c5soc: initial a5soc copy
2014-07-01 13:05:26 -04:00
e38813fa9f
fifo- monitor status signals
2014-06-25 12:15:13 -04:00
57bb3705f2
zc706-plddr3: read changes to lower dma clock
2014-06-25 09:20:58 -04:00
6ea7dd7fc3
kcu105: pwr-good added
2014-06-12 15:22:31 -04:00
2837d788a6
mitx045: Added I2S core to the base design
2014-06-06 17:53:47 +03:00
cf56a568c6
kcu105: GTH updates
2014-06-05 14:27:38 -04:00
45325b7c0d
mitx045: minor changes in common and ADV7511 projects
2014-06-03 19:24:12 +03:00
c52327d0c6
common,adv7511: Added mitx045 platform.
2014-06-02 11:08:03 +03:00
877b81a373
ad9625/vc707: working version
2014-05-30 15:07:23 -04:00
c789dce77e
ad9625/zc706: added pl ddr3 fifo changes
2014-05-29 12:59:29 -04:00
56ddce1e8c
dmac: create fifo interface to avoid being treated as axi control stream
2014-05-27 10:25:14 -04:00
f73819f4d4
zc706: pl ddr3 initial checkin
2014-05-13 16:19:53 -04:00
c5b3dd3643
vc707 base : tcl update
...
- Added missing address space
- Connect the sys_audio_clkgen/reset
2014-05-08 12:30:25 +03:00
3ac1da178e
kcu105: sane except for ddr4/ethernet
2014-05-06 15:39:05 -04:00
53af7f3c1f
ml605: initial checkin
2014-05-05 11:20:26 -04:00
4d4f66fbdd
a5soc: increase pipeline for qsys
2014-05-04 10:38:53 -04:00
a10043c4f4
kcu105: base complete with ethernet errors
2014-04-30 14:41:43 -04:00
9900a56fa5
kcu105: initial checkin
2014-04-30 14:41:37 -04:00
0b1ce14842
a5soc: basic hardware build
2014-04-30 12:40:27 -04:00
99d66e7580
a5soc: initial-copy version
2014-04-30 12:40:26 -04:00
fbfd658f0d
zc706: added pl ddr3 mig
2014-04-09 15:58:12 -04:00
04ab34c8ed
a5gt: ethernet assignments
2014-04-03 20:50:16 -04:00
d0a8b4a63c
kc705,common: Mem_interconnect maximize performance
...
For FMCOMMS1, when both the ADC and DAC DMAs are active, the system was
unstable. With this fix, it the system seems to be stable.
2014-04-03 15:59:33 +03:00
0d678b89ed
altera a5gt fmcjesdadc1 setup
2014-04-01 11:46:37 -04:00
fbafaa8507
MicroBlaze base system: Fix a few net names
...
Every interconnect interface net name follows the convention:
<interconnect name>_<interface name>
No changes in logic or any connection!
2014-04-01 10:40:35 +03:00
a881557645
base_design: Fixed AC701 and VC707 contstraints
...
AC701: Modified the IOSTANDARD for some of the pins to correspond to the
AC701 user guide.
VC707: Fixed naming for some system clocks
2014-03-31 17:38:20 +03:00
f9a67371c0
Zynq Base System: Reset is synchronized to lowest system clock
...
System reset (sys_100m_reset) is synchronized to lowest system
clock (FCLK0), via a Processor System Reset module
2014-03-26 17:58:14 +02:00
0f10623be4
AC701/VC707: Define common variables
...
Define variables sys_zynq, sys_mem_size, sys_addr_cntrl_space.
2014-03-25 14:24:51 +02:00
aa7b0bb4dd
VC707 basesys: General fixes, actual status: working
...
- Add an auxiliary cpu interconnect
- Add an auxiliary interrupt concatenation module
- Add new MIG file, current frequency of the DDR interface is 100
Mhz
- Memory interconnect optimisation strategy is 'Maximize
Performance'
2014-03-24 13:07:48 +02:00
b94acf78aa
AC701 bases sys: Add an auxiliary cpu interconnect
...
- Add an auxiliary cpu interconnect, the KC705 base system was
used as reference
- Base system is tested and working
2014-03-24 13:01:52 +02:00
792e8a208d
KC705 base system: Make a few cosmetic changes
2014-03-24 12:55:37 +02:00
8a08031dce
AC701: Modify interrupt concatenation
...
- Interrupt concatenation is the same as in case of KC705
2014-03-24 10:20:56 +02:00
13b4dd07d0
KC705 base system: Modify interrupt concatanation
...
- Add an aditional interrupt input net for the sys_concat_aux_intc
module
2014-03-21 14:45:18 +02:00
c6143dbfaf
KC705 base system: Delete trailing whitespaces.
2014-03-21 14:42:27 +02:00
3a0d1282b7
Fix the remaining issues
...
- Swap the IO locations of ports vsync and hsync
- Change the mem_interconnect optimization strategy to Maximize
Performance
2014-03-20 14:36:01 +02:00
7cdab9b5b0
Change the internal clock generator to Clock Wizard
...
- Using a Clock Wizard Module, in place of the DDR Controler's MMCM for internal clock
generation.
2014-03-18 17:24:45 +02:00
dc44703cf1
zynq/non-zynq: identical signal names and instances
2014-03-17 17:02:03 -04:00
a6da4ca01c
zynq/non-zynq merge variables
2014-03-17 16:39:52 -04:00
e1f23e7d49
Merge branch 'master' of github.com:analogdevicesinc/hdl
2014-03-11 09:58:34 -04:00
f3ae57a53e
global clock and reset names
2014-03-11 09:57:59 -04:00
75963ab376
Initial check in of VC707 base project
...
- All source files for the VC707 base project
- Update the common base system to the new naming convention
2014-03-10 17:26:17 +02:00
5c3b65d01b
adv7511: kc705/ac701 updates
2014-03-06 09:36:50 -05:00
360f10395a
initial checkin
2014-03-03 13:42:25 -05:00
3c0ea759a0
changed path settings
2014-03-03 10:06:02 -05:00
ddac1a8834
added common board files
2014-02-28 21:17:01 -05:00
Istvan Csomortani
Adrian Costina
Rejeesh Kutty
Michael Hennerich
Lars-Peter Clausen
dbogdan