Commit Graph

888 Commits (a74e2061e90d22ce959406d42bd9763d77ac0123)

Author SHA1 Message Date
Dragos Bogdan 3d3d1098b4 axi_ad7616: Default DATA_WIDTH is 8 bits 2016-01-28 16:02:01 +02:00
Istvan Csomortani 122667259f ad7616_sdz: Update Make file 2016-01-28 14:48:44 +02:00
Istvan Csomortani fbb0d368bf axi_ad7616: Add support for parallel interface 2016-01-28 12:37:22 +02:00
Istvan Csomortani cd43ebd8bc axi_ad7616: The OP_MODE parameter is no longer required 2016-01-26 11:05:33 +02:00
Istvan Csomortani 2a17ce275c axi_ad7616: Control inputs are controlled through GPIO
The following control inputs are controlled through GPIO: reset_n, seq_en, hw_rngsel, chsel, crcen, burst and os.
2016-01-25 17:50:50 +02:00
Istvan Csomortani 4b962e8d72 spi_engine: The width of the counters depend on the current DATA_WIDTH 2016-01-20 15:44:06 +02:00
Istvan Csomortani c29dd8fad5 axi_ad7616: Fix Makefile 2015-12-21 19:39:58 +02:00
Istvan Csomortani 0b55325db9 axi_ad7616: Fix IP packaging script 2015-12-21 19:39:14 +02:00
Istvan Csomortani 17e7d1b86f ad7616: Add Makefiles 2015-12-21 17:09:42 +02:00
Istvan Csomortani 8ae9de8fba axi_ad7616: Update core
+ Both the data width and number of SDI lines are configurable
+ SER1W line is hardware configurable, it was removed from the IP
+ Add 'Hardware mode' support for the controller
2015-12-14 16:00:56 +02:00
Istvan Csomortani 4e57170384 spi_engine: Update SPI Engine frame work
+ data width and number of SDI lines are configurable
+ axi_spi_engine module can have two different type of memory map interface (S_AXI or UP)
2015-12-14 15:57:54 +02:00
Istvan Csomortani 29a0f27cd1 ad_edge_detect: Add a flop to output, reset is active high 2015-12-14 15:40:29 +02:00
Istvan Csomortani d6eae81bc1 axi_ad7616: Add the control module to the core, finish up SPI integration 2015-11-13 18:14:21 +02:00
Istvan Csomortani 952a491f59 axi_ad7616: Add spi engine to the core 2015-11-12 16:12:16 +02:00
Istvan Csomortani e4927887fd spi_engine_offload: Add sync_bits to the IP files list 2015-11-10 13:35:15 +02:00
Istvan Csomortani 229cd079b9 spi_engine: Fix to support multiple SDI lines 2015-11-10 13:34:29 +02:00
Istvan Csomortani 64d1948ea0 axi_ad7616: Initial commit 2015-11-10 13:32:56 +02:00
Istvan Csomortani cf58110a98 Merge branch 'dev' into dev_ad7616 2015-11-03 14:07:48 +02:00
Lars-Peter Clausen acd9efc528 axi_hdmi_tx: Add parameter to configure the output clock polarity
In order to maximize the window where it is safe to capture data we ideally
want to launch data on the opposite edge to which it is captured. Since the
edge on which data is captured depends on the connected device add a
parameter that allows to configure the launching edge.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-11-03 10:59:13 +01:00
Istvan Csomortani a147acd791 spi_engine: Add support for multiple SDI lines.
By changing the parameter called SDI_DATA_WIDTH the spi framework can support multiple SDI lines.
The supported number of SDI lines are: 1, 2, 3 and 4.
2015-11-02 18:42:55 +02:00
Rejeesh Kutty 88568c21e1 util_gtlb: updates for latest axi_jesd_gt 2015-10-30 18:47:36 -04:00
Rejeesh Kutty 2b6ae00a44 library: add mfifo 2015-10-27 14:52:02 -04:00
Rejeesh Kutty f1ed27105f library/common- reset fix 2015-10-23 14:32:35 -04:00
Adrian Costina 32b3cfd8b9 axi_usb_fx3: Initial commit of the core with interface stub 2015-10-23 13:27:00 +03:00
Adrian Costina 9d2b8809df Makefiles: Updated Makefiles 2015-10-23 10:44:27 +03:00
Istvan Csomortani 6fb56079ee library/util_gtlb: Add Makefile 2015-10-16 13:58:01 +03:00
Istvan Csomortani 8ecdb4a4ca library/tdd_control: Add common registers to the register map and fix init value of a register
+ Software in general needs to have access to the VERSION register.
+ tdd_sync_d3 registers init value should be 1'b0
2015-10-16 11:57:54 +03:00
Rejeesh Kutty 44568f1f64 util_jesd_gt: bad idea, it is needed for ipi 2015-10-15 11:13:08 -04:00
Rejeesh Kutty a6ff1b13fc util_jesd_gt- remove unused parameters 2015-10-15 10:46:07 -04:00
Istvan Csomortani c9a5057b93 library/prcfg : Split data bus to channels
Because of the new pack/upack modules on the data path, it makes more sense to split the data interface of the PR modules into separate channels.
The top module will supports max 4 channels.
2015-10-13 11:36:45 +03:00
Adrian Costina a753d506c5 axi_mc_controller: Removed channels, as no data needs to be streamed to DMA 2015-10-09 13:54:03 +03:00
Adrian Costina 694dbd3259 axi_mc_controller: Updated constraints 2015-10-09 13:53:13 +03:00
Adrian Costina 7c3646e863 axi_mc_current_monitor: Removed stub channel 2015-10-09 13:52:14 +03:00
Adrian Costina 99e6240126 axi_mc_current_monitor: Updated constraints 2015-10-09 13:51:15 +03:00
Adrian Costina d19d9c8fbc axi_mc_speed: Corrected maximum number of channels 2015-10-09 13:50:25 +03:00
Adrian Costina ce01185348 axi_mc_speed: Updated constraints 2015-10-09 13:50:08 +03:00
Adrian Costina 96d363849e ad_dds: Registered dds_scale so that Vivado can optimally map the dsp block 2015-10-09 13:43:14 +03:00
Adrian Costina df8ac2e726 axi_ad9671: Updated constraints 2015-10-09 13:15:55 +03:00
Adrian Costina 03b225a802 axi_ad9671: Fixed synchronization mechanism 2015-10-09 13:15:12 +03:00
Istvan Csomortani 8321d5a4fb util_dacfifo: Update read out method
Update the way how the fifo push out its content. By default the fifo pushes out all its content, if an xfer_last signal is received, the fifo saves the last write address, and reads out until the saved address.
2015-10-08 17:13:12 +03:00
Rejeesh Kutty cd9754afbe up_gt: separate pll resets to tx/rx 2015-10-02 13:58:30 -04:00
Rejeesh Kutty f3ffd5a63f up_gt: separate pll resets to tx/rx 2015-10-02 13:58:30 -04:00
Rejeesh Kutty 2b894bc13e up_gt: separate pll resets to tx/rx 2015-10-02 13:58:30 -04:00
Rejeesh Kutty 5c3f90a676 up_gt: separate pll resets to tx/rx 2015-10-02 13:58:30 -04:00
Rejeesh Kutty ba70c7a4ea ad9144- ip updates 2015-09-30 11:37:10 -04:00
Rejeesh Kutty 54fcf06eed ad9152- ip updates 2015-09-30 11:34:09 -04:00
Istvan Csomortani 81a1c21553 util_pmod_adc: Reset line changed to active low reset. 2015-09-30 12:33:46 +03:00
Istvan Csomortani 97a9ecfc9a axi_hdmi_rx: Update constraint file and fix reset line 2015-09-29 18:49:30 +03:00
Istvan Csomortani b765be568f up_gt_channel: Delete the register, which stores transceiver type
Transceiver type is stored in axi_jesd_gt/up_gt only.
2015-09-29 14:23:42 +03:00
Istvan Csomortani cffb2e6226 up_gt_channel: Move the VERSION register to up_gt_channel, in order to preserve its address 2015-09-29 14:19:52 +03:00