Commit Graph

2872 Commits (a824bbfdbeea48d9d1f97f235e162087c1c799ae)

Author SHA1 Message Date
LIacob106 a824bbfdbe library/scripts/adi_ip_xilinx.tcl: remove duplicate adi_env.tcl source
Signed-off-by: LIacob106 <liviu.iacob@analog.com>
2022-08-23 17:55:27 +03:00
Iulia Moldovan e02d31cdfd scripts: Set required Vivado version only in adi_env.tcl
Signed-off-by: Iulia Moldovan <iulia.moldovan@analog.com>
2022-08-18 15:41:58 +03:00
Iulia Moldovan dde37124a4 scripts: Update Vivado version to 2021.2
Signed-off-by: Iulia Moldovan <iulia.moldovan@analog.com>
2022-08-18 15:41:58 +03:00
Ionut Podgoreanu 214cf5896e library/common: Enable automatic logging of simulation output 2022-08-10 12:00:15 +03:00
Ionut Podgoreanu 79579f65df library/common: Update the packing IPs to be more generic 2022-08-10 12:00:15 +03:00
PopPaul2021 0595f93452
AD777x support for ZedBoard and DE10Nano (#937)
* library/common: Ad adc_status_header, adc_crc_err and adc_crc_enable.

* library/axi_ad777x: Initial commit for Xilinx and Intel

* projects/ad777x_ardz: Initial commit for ZedBoard and DE10Nano
2022-08-10 11:29:05 +03:00
Laszlo Nagy ab29f21f7a axi_ltc2387: Update data formatter instance to use bits instead of octets 2022-08-08 14:22:24 +03:00
Laszlo Nagy d8a6e81c7e jesd204/ad_ip_jesd204_tpl_adc: Fix data formater for N'=12 if DMA interface is also 12 2022-08-08 14:22:24 +03:00
Iacob_Liviu 482f0489a3 scripts: Merge adi_env.tcl into a single file
Move the new adi_env.tcl file from hdl/projects/scripts into hdl/scrips
2022-08-08 13:52:54 +03:00
Filip Gherman 929f80cd31 library/jesd204: Updated jesd to support more lanes
Modified the maximum number of supported lanes up to 32 lanes for every JESD layer

Signed-off-by: Filip Gherman <Filip.Gherman@analog.com>
2022-08-04 13:10:53 +03:00
Laszlo Nagy 7a48f1beb9 util_do_ram: Fix Rx path for interrupted transfers
When capture length is not programmed the DMA will interrupt the
transfer once it received all the samples he was set in its descriptor,
this case must be handled by resetting the read process and returning
an end of transfer (eot) to the data offload control logic.
2022-08-04 09:45:52 +03:00
Laszlo Nagy 1d4b27ea8c util_axis_fifo_asym: Fixes for simulation
Initialization of regs was not executed in always(*) blocks since
the block is not triggered due missing inputs.
2022-08-04 09:45:52 +03:00
Laszlo Nagy 4982104982 data_offload: Fix Tx bypass
Tx path was gated by the FSM also in bypass mode. This must be avoided
since the bypass mode should be independent of the FSM.

Write to bypass fifo only when bypass is enabled
2022-08-04 09:45:52 +03:00
Laszlo Nagy bdaa0f086b data_offload: Increase bypass FIFO size 2022-08-01 12:47:26 +03:00
LIacob106 472f41ad2c ad_ip_jesd204_tpl_adc_hw.tcl: Add 14 bit option for converter resolution 2022-07-25 14:14:28 +03:00
Iulia Moldovan 0c0617d49e libraries: Update modules according to guideline
* Added header license for the files that didn't have
* Modified parentheses
* Removed extra spaces at the end of lines
* Fixed parameters list to be each parameter on its line
* Deleted lines after endmodule and consecutive empty lines
* Fixed indentation

Signed-off-by: Iulia Moldovan <iulia.moldovan@analog.com>
2022-06-28 18:06:56 +03:00
Adrian Costina 9357b0c987 axi_ltc2387: Intial commit 2022-05-18 18:23:38 +03:00
Benjamin Menkuec 56a65b717c mark axi_gpreg.v as systemverilog, otherwise it gives an error with vivado 2022.1 2022-05-17 21:13:11 +03:00
Mathias Tausen cd04141ffd axi_dmac: Add parameter controlling AWCACHE
On architectures with ports that support cache coherency, the AWCACHE
signal must be set to indicate that transactions are cached. This patch
adds a parameter allowing AWCACHE to be set on an AXI4 destination port.
2022-05-10 11:50:55 +03:00
Filip Gherman 302e59e109 data_offload_constr.ttcl: Fix false_paths for i_sync_src_transfer_length registers 2022-05-10 09:46:03 +03:00
Ionut Podgoreanu faf5f90299 library/axi_dmac: Add the BYTES_PER_BURST_WIDTH interface parameter in INTERFACE_DESCRIPTION 2022-05-06 12:32:41 +03:00
PopPaul2021 619e8043d0
Adaq8092 on ZedBoard LVDS output mode (#921)
* common/up_adc_common: Add adc_custom_control register

* library/axi_adaq8092: Initial commit

* projects/adaq8092_fmc: Initial commit for ZedBoard
2022-04-28 15:39:59 +03:00
Laszlo Nagy 97b92565b2 Makefile: Replace util_fifo2axi_bridge with util_hbm 2022-04-28 14:31:32 +03:00
Laszlo Nagy 8399301c6a util_fifo2axi_bridge: Deprecate module, replaced by util_hbm 2022-04-28 14:31:32 +03:00
Laszlo Nagy c3ae609bc8 data_offload: Refactor core
Deprecate unused parameters.

Change to MEM_SIZE_LOG2, to support only power of 2 storage sizes for
now. However in the future we might want to add support for non pow2
sizes so register map is not changed.

Change transfer length to -1 value to spare logic.

Change FIFO interface to AXIS to have backpressure, this allows the
implementation of data movement logic in the storage unit and let the
FSM handle high level control an synchronization and control the storage
unit through a control interface.

Refactor FSM to have preparation states where slow storages can be
configured and started ahead of the data handling.

Make bypasss FIFO optional since in some cases causes timing failures
due the missing output register of the memory. This can be targeted in
a later commit.

Hook up underflow/overflow to regmap useful in case of external memory
where rate drops due misconfiguration can be detected.

Cleanup for verilator.

Scripting:
Add HBM and DDR external memory support using util_hbm IP
Replace asym_block_ram with util_do_ram IP
2022-04-28 14:31:32 +03:00
Laszlo Nagy 35d32e0143 util_do_ram: Initial version
This IP replaces the ad_mem_asym module as storage element for the data
offload.
Having standard AXIS interface for data will allow
implementation of storages on UltraRAM.
2022-04-28 14:31:32 +03:00
Laszlo Nagy 3209b9d840 interfaces: Data offload control interface
Have a control interface between the data offload and storage units.
2022-04-28 14:31:32 +03:00
Laszlo Nagy 3bf7b6c80f util_hbm: Initial version
This IP serves as storage interfacing element for external memories like
HBM or DDR4 which have AXI3 or AXI4 data interfaces.

The core leverages the axi_dmac as building blocks by merging an array of
simplex DMA channels into duplex AXI channels. The core will split the
incoming data from the source AXIS interface to multiple AXI channels,
and in the read phase will merge the multiple AXI channels into a single
AXIS destination interface.
The number of duplex channels is set by syntheses parameter and must be
set with the ratio of AXIS and AXI3/4 interface.

Underflow or Overflow conditions are reported back to the data offload
through the control/status interface.

In case multiple AXI channels are used the source and destination AXIS
interfaces widths must match.
2022-04-28 14:31:32 +03:00
David Winter 6be4ea92a7 library: axi_tdd: Make synchronization stage optional
Signed-off-by: David Winter <david.winter@analog.com>
2022-04-20 10:54:53 +03:00
David Winter 73468d662b axi_tdd: Add false paths to tdd sync input
This allows the external synchronization input to be driven from
asynchronous sources like a 1 PPS signal or just signals from different
clock domains in general.

Signed-off-by: David Winter <david.winter@analog.com>
2022-04-20 10:54:53 +03:00
Iulia Moldovan 63089a7c5d library/axi_ad9361/intel: Update I/O format 2022-04-08 11:00:04 +03:00
Iulia Moldovan 7a5ecb592e library/data_offload: Remove empty module data_offload_control 2022-04-07 17:17:47 +03:00
Adrian Costina 18b5fabde0 library: Remove unused IPs 2022-04-06 14:57:37 +03:00
AndrDragomir 60be01f2eb axi_clock_monitor: Fix various issues
- Replace .xdc file
- Remove parameter dependency for wire signals
- Fix typo
- Remove unnecessary comments
- Fix signal width
2022-04-05 12:23:33 +03:00
Iulia Moldovan fe713a5e98 library/axi_dmac: Rename 2d_transfer to dmac_2d_transfer
Update the file according to HDL guideline.
Replace all occurrences of 2d_transfer with dmac_2d_transfer.
Update axi_dmac/Makefile.
2022-04-01 16:02:46 +03:00
Iulia Moldovan d9ec44657f libraries: Correct module name according to the filename 2022-04-01 16:02:46 +03:00
PopPaul2021 0d44bfb4dd
axi_hdmi_tx update for: ZedBoard, ZC706, ZC702, de10nano, ADRV9361-Z7035 (#897) 2022-03-29 16:51:21 +03:00
Adrian Costina de70157e3a xilinx/common:ad_data_out.v: Fix typo 2022-03-29 16:50:20 +03:00
AndrDragomir 204dff3b73 library: Adding axi_clock_monitor ip core 2022-03-29 10:02:42 +03:00
Adrian Costina 31c21cad7f xilinx/common: Add CLKEDGE parameter to ad_data_* module 2022-03-25 15:10:12 +02:00
Nick Pillitteri c1721e18dd account for ADI_VIVADO_IP_LIBRARY global variable when adding subcores 2022-03-24 16:29:49 +02:00
alin724 6a252ec067 util_mii_to_rmii: Fix 100 Mbps configuration functionality 2022-03-22 14:30:24 +02:00
Nick Pillitteri 084d44c978 add ability to customize Xilinx IP library version to value other than "user" from a global variable. 2022-03-17 09:43:39 +02:00
Laszlo Nagy e66c5282bc axi_adrv9001: Expose IODELAY_CTRL parameter to top level 2022-03-02 11:06:12 +02:00
Laszlo Nagy 4c7be950d1 ad_ip_jesd204_tpl_adc: Fix latency of valid signal 2022-02-16 10:27:50 +02:00
Laszlo Nagy f245448976 ad_ip_jesd204_tpl_ : Add missing dependency 2022-02-07 19:14:01 +02:00
Laszlo Nagy b5092662d5 ad_ip_jesd204_tpl_adc: Refactor external sync
- Add EXT_SYNC option
- Gate valid while in reset
2022-02-07 19:14:01 +02:00
Laszlo Nagy 8c7cca4277 common/up_adc_common: Add ext sync regs 2022-02-07 19:14:01 +02:00
Laszlo Nagy 1b06c74919 common/up_dac_common: Add manual sync request 2022-02-07 19:14:01 +02:00
Laszlo Nagy db49aa652f common/up_dac_common: Add support for explicit disarm control 2022-02-07 19:14:01 +02:00