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6235 Commits (a824bbfdbeea48d9d1f97f235e162087c1c799ae)

Author SHA1 Message Date
Iacob_Liviu 7dae0858b0 de10nano: changed quartus version to 20.1.1 2022-01-31 14:10:51 +02:00
AndreiGrozav 38f3627695 ad_dds: Fix DDS start samples 
When using a CLK_RATIO > 1 the first n samples(n=CLK_RATIO) after sync, are
noisy. This is because the phase accumulator data is passed to the phase to
amplitude converter, during the phase synchronization step.
 2022-01-31 14:07:11 +02:00
sergiu arpadi bc5974d789 ad77681evb: Fix irq overlap 
spi engine irq signal was overwriting fmc iic irq
 2022-01-31 12:32:31 +02:00
Dan Hotoleanu f34b561e19 daq3: Parameterize JESD204 configuration values 
Added the capability to set the JESD204 configuration values from a single
point in the code and to modify these default settings from the command
line for the Xilinx FPGAs in the project.

Signed-off-by: Dan Hotoleanu <dan.hotoleanu@analog.com>
 2022-01-31 10:47:01 +02:00
Dan Hotoleanu e8ff32d6df ad6676evb: Parameterize JESD204 configuration values 
Added the capability to set the JESD204 configuration values from a single
point in the code and to modify these default settings from the command
line for the Xilinx FPGAs in the project.

Signed-off-by: Dan Hotoleanu <dan.hotoleanu@analog.com>
 2022-01-31 10:36:31 +02:00
Dan Hotoleanu 318523579f ad6676evb: Update to JESD204 TPL instantiation 
Updated the JESD204 TPL instantation of the design.

Signed-off-by: Dan Hotoleanu <dan.hotoleanu@analog.com>
 2022-01-31 10:36:31 +02:00
Iulia Moldovan b26b4c00f0 ad9783: Clean-up parameters and module instances 2022-01-25 18:24:43 +02:00
Iulia Moldovan 9ca5ae07b2 ad9783: Add Readme.md 2022-01-25 17:16:30 +02:00
Laszlo Nagy 889447e900 axi_ad9361: make IODELAYCTRL insertion optional 2022-01-25 09:50:31 +02:00
Laszlo Nagy bc8e7881f2 axi_dmac: Hook up ID 
Signed-off-by: Laszlo Nagy <laszlo.nagy@analog.com>
 2022-01-25 09:50:22 +02:00
Dan Hotoleanu 530aca9754 daq2: Parameterize JESD204 configuration values 
Added the capability to set the JESD204 configuration values from a single
point in the code and to modify these default settings from the command
line for the Xilinx FPGAs in the project.

Signed-off-by: Dan Hotoleanu <dan.hotoleanu@analog.com>
 2022-01-20 12:54:03 +02:00
Iulia Moldovan f3cf7508c8 ad9783: Update Makefile 2022-01-20 12:31:57 +02:00
Filip Gherman 4ec8797c7c adrv9009: Parameterize JESD204 configuration values 2022-01-13 10:15:05 +02:00
LIacob106 9d94f21d89 scripts/adi_xilinx_device_info_enc.tcl: Change regex for vcu128 
The regex does not match vcu128 as Ultrascale+. It matches for Ultrascale.
 2022-01-12 17:32:47 +02:00
Filip Gherman 6a92bd5925 adrv9371x: Parameterize JESD204 configuration values 2022-01-12 16:05:48 +02:00
Filip Gherman d8a418d8d0 projects/scripts/adi_board/tcl: Updated ad_xcvrcon procedure for parametrized projects 2022-01-12 16:05:18 +02:00
Filip Gherman 9d8097389c library/jesd204/jesd204_common/pipeline_stage.v: Initialize pipeline stage register 2022-01-12 13:43:20 +02:00
sergiu arpadi fc04198b2b adrc9361_ccfmc: Fix SFP pin locations 2022-01-12 13:43:06 +02:00
Dan Hotoleanu 86d2467f57 fmcjesdadc1: Parameterize JESD204 configuration values 
Added the capability to set the JESD204 configuration values from a single
point in the code and to modify these default settings from the command
line.

Signed-off-by: Dan Hotoleanu <dan.hotoleanu@analog.com>
 2022-01-12 13:28:42 +02:00
Filip Gherman 080925e8fe library/jesd204: tpl timing bug fix 2022-01-12 10:14:55 +02:00
Iulia Moldovan 3d000ee6a8 ad9783_zcu102_dev: Initial commit 2022-01-07 14:04:08 +02:00
Iulia Moldovan 08f029c757 axi_ad9783: Initial commit 2022-01-07 14:04:08 +02:00
David Winter fcd3bfd349 util_pulse_gen: Reload registers when counter is at one 
This patch fixes an issue where the pulse width is only updated two
periods after the current one.

Signed-off-by: David Winter <david.winter@analog.com>
 2022-01-04 15:02:05 +02:00
Filip Gherman 6dddaaaa78 adrv9009zu11eg/adrv2crr_xmicrowave: Update Makefile 2021-12-22 11:33:15 +02:00
Stanca Pop 0d45f4dc94 xmicrowave: Fix typo 2021-12-17 15:44:23 +02:00
AndreiGrozav c2d960e029 axi_adrv9001: Add external sync support 
The external sync must be synchronous to the reference clock, in order
to obtain a deterministic synchronization of the interface.
 2021-12-16 15:16:30 +02:00
LIacob106 38c489d254 projects: set Quartus version for cyclone5, cn0506_mii and cn0506_rgmii 2021-12-15 17:13:38 +02:00
Dan Hotoleanu fb17147eb4 fmcadc2: Parameterize JESD204 configuration values 
Add the capability to set the JESD204 configuration values from a single
point in the code and to modify these default settings from the command
line.

Signed-off-by: Dan Hotoleanu <dan.hotoleanu@analog.com>
 2021-12-10 20:54:39 +02:00
Dan Hotoleanu 13a282d9c4 fmcadc2: Update JESD204 TPL instance 
Updated the JESD204B transport layer instance to instantiate the new TPL IP
module.

Signed-off-by: Dan Hotoleanu <dan.hotoleanu@analog.com>
 2021-12-10 20:54:39 +02:00
Laszlo Nagy 41525f348b axi_adrv9001/axi_adrv9001_core.v: Disable TDD and IOCTRL if second SSI interface is disabled 2021-12-08 17:31:53 +02:00
Laszlo Nagy dfe153dc68 axi_adrv9001/axi_adrv9001_tdd.v: Add disable option for TDD 2021-12-08 17:31:53 +02:00
Laszlo Nagy 8cc0367e8f axi_adrv9001: Hide disabled interfaces 
Signed-off-by: Laszlo Nagy <laszlo.nagy@analog.com>
 2021-12-08 17:31:53 +02:00
Laszlo Nagy 6a4b46ebb4 axi_adrv9001: Make Rx2 and Tx2 source synchronous interfaces optional 
If the Rx2 and Tx2 SSI are disabled the rx1,tx2 data paths are forced to
R1 mode.

Signed-off-by: Laszlo Nagy <laszlo.nagy@analog.com>
 2021-12-08 17:31:53 +02:00
Dan Hotoleanu 77f3e5155b ad9081_fmca_ebz: Fix signal length parameter 
Corrected the length parameter for the rx_data input.

Signed-off-by: Dan Hotoleanu <dan.hotoleanu@analog.com>
 2021-12-08 14:29:48 +02:00
stefan.raus 040d5732c7 README.md: Add link to boot partition files download link 
Add in README.md how to use and from where to get already built boot files.

Signed-off-by: stefan.raus <stefan.raus@analog.com>
 2021-12-07 14:42:42 +02:00
Laszlo Nagy 1b8ca5f045 fmcjesdadc1: bd: Clean trailing white spaces and alignment 
Signed-off-by: Laszlo Nagy <laszlo.nagy@analog.com>
 2021-12-03 16:10:51 +02:00
Laszlo Nagy 8e226282cd fmcjesdadc1: bd: Replace hardcoded lane number with parameter 
Signed-off-by: Laszlo Nagy <laszlo.nagy@analog.com>
 2021-12-03 16:10:51 +02:00
Laszlo Nagy 80b3fc2d0a ad9081_fmca_ebz: versal: Remove unused GT reset input pin 
Signed-off-by: Laszlo Nagy <laszlo.nagy@analog.com>
 2021-11-22 16:18:29 +02:00
Laszlo Nagy 1ec0993d33 ad9081_fmca_ebz/vcu128: Remove ref clock replica 
Signed-off-by: Laszlo Nagy <laszlo.nagy@analog.com>
 2021-11-22 16:18:29 +02:00
sergiu arpadi c1ca578343 axi_ad7616: Fix sync port 2021-11-22 15:22:16 +02:00
Stanca Pop 2a740d0c2b ad7616_sdz: Add make env argument for interface 
Update system_project.tcl
 2021-11-22 15:22:16 +02:00
Stanca Pop c2d37b2db3 pulsar_adc_pmdz: Initial commit 2021-11-22 13:39:17 +02:00
PopPaul2021 c71e5de928
zcu102: ad_fmclidar1_ebz, fmcomms5, fmcomms8 (#811) 
adrv2crr_fmc: adrv9009zu11eg
adrv2crr_xmicrowave: adrv9009zu11eg

The IBUFGDS primitive is deprecated in UltraScale devices.
 2021-11-22 08:09:46 +02:00
Laszlo Nagy 8e0a45dea9 jesd204_rx/jesd204_lane_latency_monitor.v: Fix for datapath width of 4 
Current implementation is correct only for datapath width of 8.
The buswidth of latency measurement inside a beat has a fixed width (3 bits)
for each lane that must be taken in account when computing the total latency.

Signed-off-by: Laszlo Nagy <laszlo.nagy@analog.com>
 2021-11-19 18:14:43 +02:00
Laszlo Nagy 3cd203e9c7 scripts/adi_board.tcl: improvements for vcu128 DDR controller 
- allow specifying the name of Axi Lite interface from the peripheral were to connect the control bus
- some DDR controllers have an Axi Lite control interface, this creates
  a second address segment which causes issues, differentiate the memory
  segment from control registers segment
 2021-11-19 18:08:16 +02:00
Laszlo Nagy e76f287e73 ad9081_fmca_ebz:vcu128: Initial version 
* 4Txs / 4Rxs per MxFE
 * Tx I/Q Rate: 250 MSPS
 * Rx I/Q Rate: 250 MSPS
 * DAC JESD204B: Mode 9, L=4, M=8, N=N'=16
 * ADC JESD204B: Mode 10, L=4, M=8, N=N'=16
 * DAC-Side JESD204B Lane Rate: 10Gbps
 * ADC-Side JESD204B Lane Rate: 10Gbps
 2021-11-19 18:08:16 +02:00
Laszlo Nagy 88b5c2d6db projects/common/vcu128: Initial VCU128 support 2021-11-19 18:08:16 +02:00
Laszlo Nagy e00def31d0 ad9081_fmca_ebz: versal: Remove external gt_reset logic 2021-11-19 14:01:48 +02:00
Laszlo Nagy 0b9631f1f7 ad9081_fmca_ebz: versal: Rename nets 2021-11-19 14:01:48 +02:00
Laszlo Nagy ca6248ba88 ad9081_fmca_ebz/common/versal_transceiver.tcl: Reset also PLL 2021-11-19 14:01:48 +02:00