Commit Graph

282 Commits (a9c61485704d74723c48cf0bad03056ecfc8e4e4)

Author SHA1 Message Date
Lars-Peter Clausen b3657b77cb util_sync_reset: Fix polarity of the sync_resetn signal
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-03-25 13:03:12 +01:00
Lars-Peter Clausen a230e6505a axi_dmac: Add option to configure AXI standard 2014-03-25 12:47:27 +01:00
Lars-Peter Clausen d0e26899a4 Add util_sync_reset helper module
This helper module can be used to make sure that a reset signal is de-asserted
synchronously to a clock signal. This is e.g. required by the AXI spec.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-03-24 22:43:01 +01:00
Rejeesh Kutty ef960a29c7 altera files 2014-03-24 13:27:27 -04:00
Adrian Costina 551319a670 Modified data mover to improve timing 2014-03-20 18:22:18 +02:00
Lars-Peter Clausen e373b85954 axi_dmac: Fix Vivado warnings
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-03-18 20:59:13 +01:00
Lars-Peter Clausen 29d590c951 axi_dmac: response_generator: Do not generate responses during ID sync
During an ID sync the request_id might increment, we should not generate a
response in this case. Since the ID sync only happens when the core is disabled
check that the core is enabled before generating a response.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-03-18 19:12:13 +01:00
Lars-Peter Clausen df1c4f0786 axi_dmac: data_mover: Improve timing
The pending_burst signal and the expression id != request_id are almost
identical. pending_burst goes high with a delay of one clock cycle, but the
important thing is that it goes low on the same clock cycle as the expression.
By using pending_burst here instead of 'id != request_id' we can reduce the
fanout of the 'id' register and improve the timing of the core.
2014-03-18 19:06:26 +01:00
Lars-Peter Clausen 522a222d3a axi_dmac: Fix default value for DMA type
Vivado doesn't handle the case where we use symbolic constants for the default
value properly, so update this to use plain integers.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-03-17 13:20:49 +01:00
Rejeesh Kutty ad491e92ab changed pcore version and made it local (top shouldn't override) 2014-03-14 12:02:16 -04:00
Lars-Peter Clausen f02ba999ae axi_dmac: Add support for DMA bus widths other than 64 bit
There were a few place in the core where it assumed a 64-bit wide bus. Make this
configurable using parameters. The patch also adds support for having different
DMA bus widths on the source and destination side.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-03-13 13:20:10 +01:00
Rejeesh Kutty fd14607da5 mult instances: consistent naming style 2014-03-12 15:42:47 -04:00
Rejeesh Kutty 64a89ff66b Merge branch 'master' of github.com:analogdevicesinc/hdl 2014-03-12 15:36:00 -04:00
Rejeesh Kutty 7fc5b8ecd9 common: use dsp slice for multiply modules 2014-03-12 15:35:21 -04:00
Istvan Csomortani ba484999b3 Fix default value of $ad_hdl_dir and $ad_phdl_dir 2014-03-12 18:18:47 +02:00
Rejeesh Kutty cda3cb3280 removed misc stuff 2014-03-12 11:02:53 -04:00
Adrian Costina 92aaf0bd51 FMCOMMS1: Updated projects and axi_ad9643 core
ZC702: Removed invalid address segments. Changed the constraints
for adc_clk to minimum possible value in order to meet timing.

ZED: Change the constraints for adc_clk to minimum possible value, in
order to meet timing

AXI_AD9643: Corrected the number of bits in the adc_mon_data bus
2014-03-12 16:23:41 +02:00
Rejeesh Kutty 580808e146 axi_ad9361: added 2014-03-11 20:01:55 -04:00
Rejeesh Kutty a76d6c4686 library/axi_ad9122,axi_ad9643: added 2014-03-11 12:13:25 -04:00
Rejeesh Kutty e1f23e7d49 Merge branch 'master' of github.com:analogdevicesinc/hdl 2014-03-11 09:58:34 -04:00
Rejeesh Kutty 0817973cc0 library: removed xilinx dc filter and dds 2014-03-10 14:52:48 -04:00
Rejeesh Kutty f9dfd944c9 library/util_fifo: updates for read side 2014-03-10 14:48:14 -04:00
Rejeesh Kutty a6d747411e util_wfifo: ip cleanup 2014-03-10 11:21:20 -04:00
Rejeesh Kutty bb0431d3e8 library: dds and dcfilter changes, added fifo wrappers 2014-03-10 11:11:50 -04:00
Rejeesh Kutty d6256e9e29 library: dds and dcfilter changes, added fifo wrappers 2014-03-10 11:11:16 -04:00
Lars-Peter Clausen 8326022adc axi_dmac: address_generator: Fix disable race condition
If the address generator is disabled the very same cycle as it tries to put a
new address on the bus, it will keep sending this address forever and the core
will lock up

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-03-07 18:40:49 +01:00
Lars-Peter Clausen 6da9c65a08 axi_dmac: Add support for zero latency transfer switching
Right now there is always a period of one clock cycle where we can not transfer
any data when switching between two transfers. This patch modifies the data
mover to allow for zero latency. This fixes problems on the FMCOMMS1 platform

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-03-07 18:39:20 +01:00
Rejeesh Kutty 23a62a92b2 up_adc_common: dma bus width is 0x8 (constant) 2014-03-06 19:22:19 -05:00
Adrian Costina 831c19ea84 Added axi_dmac, axi_fifo and misc files in library 2014-03-06 18:16:02 +02:00
Rejeesh Kutty 63bd2b870a pointers to directories 2014-02-28 16:58:30 -05:00
Rejeesh Kutty ff5021b1a8 pointers to directories 2014-02-28 16:57:19 -05:00
Rejeesh Kutty f7c9368abc initial checkin 2014-02-28 14:26:22 -05:00