Rejeesh Kutty
|
aa2aa902bf
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ad9361- a10soc updates
|
2016-04-29 10:17:35 -04:00 |
|
Rejeesh Kutty
|
f411d29e30
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ad9361- a10soc changes
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2016-04-29 10:17:35 -04:00 |
|
Rejeesh Kutty
|
3563c2212c
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common/altera- removed dcfilt/mul
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2016-04-29 10:17:35 -04:00 |
|
Rejeesh Kutty
|
0260280db1
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common/altera- data path
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2016-04-29 10:17:35 -04:00 |
|
Rejeesh Kutty
|
ed62101308
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common/altera: primitives
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2016-04-29 10:17:35 -04:00 |
|
Rejeesh Kutty
|
779d014750
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ad9361-common alt/xil interface
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2016-04-29 10:17:35 -04:00 |
|
Rejeesh Kutty
|
664ea16a0f
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ccpci- carrier changes
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2016-04-27 16:26:11 -04:00 |
|
Rejeesh Kutty
|
e790e4c3ae
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a10soc- complete qsys
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2016-04-25 12:56:19 -04:00 |
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Rejeesh Kutty
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bfa6fe2a40
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a10soc- updates
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2016-04-25 11:23:16 -04:00 |
|
Rejeesh Kutty
|
28159aeec9
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a10soc- updates
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2016-04-25 11:11:46 -04:00 |
|
Rejeesh Kutty
|
0a3967b886
|
a10soc- updates
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2016-04-25 10:53:26 -04:00 |
|
Rejeesh Kutty
|
d36d1263c5
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a10soc- updates
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2016-04-25 10:50:09 -04:00 |
|
Rejeesh Kutty
|
2a5f31d26b
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fmcomms2/a10soc- copy
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2016-04-22 15:15:44 -04:00 |
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Rejeesh Kutty
|
82c4f75f13
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a10soc- a10gx copy
|
2016-04-22 10:39:21 -04:00 |
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Rejeesh Kutty
|
7a4a7edfba
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daq2/a10gx: 10AX115S3F45E2SGE3 version
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2016-04-20 16:07:41 -04:00 |
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Rejeesh Kutty
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e00236e5fd
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daq2/a10gx: 10AX115S3F45E2SGE3 version
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2016-04-20 16:04:46 -04:00 |
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Rejeesh Kutty
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8b2542b181
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daq2/a10gx: 10AX115S3F45E2SGE3 version
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2016-04-20 16:01:12 -04:00 |
|
Rejeesh Kutty
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e9b199959a
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library/adcfifo- constraints update
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2016-04-20 15:57:25 -04:00 |
AndreiGrozav
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679d471d75
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Merge branch 'hdl_2016_r1' into dev
hdl_2016_r1 contains IP core upgrades to Vivado 2015.4.2 and hdmi_tx improvements.
|
2016-04-19 18:05:50 +03:00 |
Adrian Costina
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402253d308
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usb_fx3: Updated design to include the GPIF II interface
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2016-04-19 15:52:30 +03:00 |
|
Adrian Costina
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d7d8b2cf1c
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axi_usb_fx3: Integrated actual GPIF II interface, with 2 address lines
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2016-04-19 14:38:26 +03:00 |
Istvan Csomortani
|
8a574cd8ba
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zc706_system_plddr3.tcl : Add integration process for the AXI_DAC_FIFO
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2016-04-19 11:30:52 +03:00 |
|
Istvan Csomortani
|
e855ef38f4
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axi_dacfifo: Initial commit
AXI DAC fifo, which use the PL side DDR memory. The minimum data granularity is 1kbyte.
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2016-04-19 11:28:33 +03:00 |
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Istvan Csomortani
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42cd05ab19
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ad_mem_asym: Add support for more ratios.
Supported ratios: 1:1/1:2/1:4/1:8/2:1/4:1/8:1
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2016-04-19 11:18:30 +03:00 |
|
AndreiGrozav
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c291f8f107
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daq1: Updated design to 2015.4
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2016-04-14 23:36:47 +03:00 |
|
AndreiGrozav
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469b4ea5e8
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fmcadc5: Updated design to 2015.4
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2016-04-14 23:18:23 +03:00 |
|
AndreiGrozav
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62bd057106
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fmcadc5/common: Update common design to 2015.4
|
2016-04-14 23:01:38 +03:00 |
|
AndreiGrozav
|
6fe41ebb08
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axi_hdmi_tx: Upgrade hdmi clipping process
-added two registers that control the clipping ranges (0x01a and 0x01b)
-extend clipping process for all output data formats
|
2016-04-12 22:01:07 +03:00 |
|
Istvan Csomortani
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69d721526a
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util_dacfifo: Add constraints file
|
2016-04-12 13:21:50 +03:00 |
|
Rejeesh Kutty
|
a88ced8136
|
pzsdr1: lvds/cmos updates
|
2016-04-11 16:18:29 -04:00 |
|
Rejeesh Kutty
|
3006c5a223
|
make updates
|
2016-04-11 16:14:59 -04:00 |
|
Rejeesh Kutty
|
736bbdd95a
|
pzsdr1- io updates
|
2016-04-11 16:12:21 -04:00 |
|
Rejeesh Kutty
|
8a5a5082f3
|
pzsdr1- io updates
|
2016-04-11 16:12:09 -04:00 |
|
Rejeesh Kutty
|
8e689f4594
|
pzsdr1- lvds/cmos constraints
|
2016-04-11 16:00:18 -04:00 |
|
Rejeesh Kutty
|
7e807d83b1
|
pzsdr1- cmos mode
|
2016-04-11 15:58:29 -04:00 |
|
Rejeesh Kutty
|
bf6ef4e5f3
|
board- add disconnect
|
2016-04-11 15:33:00 -04:00 |
|
Rejeesh Kutty
|
68bc647472
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pzsdr1- ddr board delays update
|
2016-04-06 15:30:27 -04:00 |
|
Istvan Csomortani
|
7b01cd9eca
|
README.md: Update the README
|
2016-03-31 19:42:52 +03:00 |
|
AndreiGrozav
|
21208ca208
|
Makefiles: Update Makefiles
|
2016-03-31 12:37:47 +03:00 |
|
Istvan Csomortani
|
1fab6ce477
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daq2/common: Add util_dacfifo/dac_xfer_out control
|
2016-03-29 16:55:33 +03:00 |
|
Istvan Csomortani
|
255b0ebd40
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util_dacfifo: Add dac_xfer_out control
The dac_xfer_out control signal is asserted while the DAC reads back data. Should be connected to upack/dma_xfer_in.
|
2016-03-29 16:50:00 +03:00 |
|
Adrian Costina
|
657144d9a7
|
a10gx: Updated base design and DAQ2 to the new revision of the a10gx board
- tried using ATX PLL and fPLL for TX transceiver clocks, but could not get them to lock
- CMU PLL works correctly as temporary solution
|
2016-03-28 13:21:36 +03:00 |
|
AndreiGrozav
|
7c2f34549b
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motcon2_fmc: Update common design to 2015.4
|
2016-03-23 10:27:07 +02:00 |
|
AndreiGrozav
|
b31cdac6bd
|
util_gmii_to_rgmii: Updated to 2015.4
The Xilinx interface changed its name from gmii_rtl_1 to gmii_rt_1
|
2016-03-23 10:14:18 +02:00 |
|
Rejeesh Kutty
|
46eddd04be
|
library: port updates on mmcm
|
2016-03-22 12:50:59 -04:00 |
|
Rejeesh Kutty
|
de4da6726b
|
axi_clkgen: port updates on mmcm
|
2016-03-22 12:50:59 -04:00 |
|
Rejeesh Kutty
|
74408881c6
|
axi_ad9122: optional clock out control
|
2016-03-22 12:50:59 -04:00 |
|
Rejeesh Kutty
|
65b2e51958
|
common/mmcm: add another clock
|
2016-03-22 12:50:59 -04:00 |
|
AndreiGrozav
|
769fecbe00
|
axi_i2s_adi: Fixed clock association
|
2016-03-21 20:18:45 +02:00 |
|
Istvan Csomortani
|
373481360b
|
util_dacfifo: Add a bypass option to the FIFO
|
2016-03-21 14:14:43 +02:00 |