Revert AXI bus signals back to upper case on SPI Engine Offload IP,
changed on e2ca5a991a.
Fixup signals from sd*_data_* to sd*_* for spi_engine_ctrl interface.
Non-breaking mistake, but added warnings to the IP.
Signed-off-by: Jorge Marques <jorge.marques@analog.com>
* SPI Engine: Add registers for Offload memory and FIFO sizes
Adds registers at dword 0x04 and 0x05, respectively allowing software
to get the sizes of the Offload Module memories (command and sdo) or
the sizes of the FIFOs on the AXI regmap.
Signed-off-by: Laez Barbosa <laez.barbosa@analog.com>
* AD7768_zed: Fix wideband filter bug
In SPI control mode, when not used as GPIO the FILTER pin and when a
crystal is used as the clock source, this pin must be set to 1.
The START pin must be tied to a logic 1 through a pull-up resistor, when
it is not used.
Use tcl script instead of static xmls for the interface.
Easier to maintain and are not gitignored.
Rename spi_master to spi_engine because every interface should be
prefixed by the IP name; in this case, spi_engine.
Also, remove interface/*.sv files on make clean and git ignore them.
Signed-off-by: Jorge Marques <jorge.marques@analog.com>
The extensions have been moved to docs tools.
The source code is available at
https://github.com/analogdevicesinc/doctools
And is installed as before:
(cd docs ; pip install -r requirements.txt --upgrade)
Since the package is listed on the requirements.txt file.
Also, add index for library and projects
Signed-off-by: Jorge Marques <jorge.marques@analog.com>
* Value 24 was wrongfully set for parameter LENGTH_WIDTH, because
it is not among the valid values, which are 28, 29, ..., 34. Set '28'
to be the default value
* Vivado Tcl somehow didn't accept the old expression set for
calculating the HBM_SEGMENTS_PER_MASTER parameter, so it was changed
accordingly to work. Dropped "expr", ".0" and "int ()" parsing and now
it works
Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
The introduction of sysid IPs on some Stratix 10 projects introduced a
problem where they would fail to build, due to mem_init_sys_file_path
not being defined. This is fixed now.
Signed-off-by: Laez Barbosa <laez.barbosa@analog.com>
* SPI Engine: fix early sdi data clear
In case an SPI read was immediately followed by a cs assert, the sdi
register was being cleared one cycle too soon, so that the data being
passed on was always 'b0.
Signed-off-by: Laez Barbosa <laez.barbosa@analog.com>
Previous level-based trigger could cause issues in some low
sampling rate setups. This commit changes it to edge-based.
Signed-off-by: Laez Barbosa <laez.barbosa@analog.com>
The lack of the create_xgui_files causes Vivado to exit with an error
when running multiple Vivado instances (parallel make case)
Signed-off-by: Jorge Marques <jorge.marques@analog.com>
Set validation ranges for DATA_WIDTH and NUM_OF_CS for the expected
min/max values in the verilog source code.
Also, fix swapped description for CPHA in the documentation.
Signed-off-by: Carlos Oliveira <caosjr8@gmail.com>
Previously when issuing a load_config, each pwm channel
was stopped in its tracks and waited for an external sync,
if that was active, or load_config release.
The desired behaviour is to wait for the pwm channels to finish
their events from the current period, before a new aligned start.
Also, the first positive edge of each pulse was initiated only
in the second pwm channel period.
This niche behaviours have not affected any functionality in the
long term alignments for current setups.
Signed-off-by: AndreiGrozav <andrei.grozav@analog.com>
When leaving the offset equal to zero for a pwm
channel. That pwm channel was not waiting for all
channels to get in sync after a load config.
Signed-off-by: AndreiGrozav <andrei.grozav@analog.com>
Drop shell for loops in favor of makefile pattern rules,
so make can run targets in parallel using -j.
This doesn't affect Vivado's own settings.
As a benchmark, 12th Gen Intel(R) Core(TM) i9-12900H 5GHz(max):
$ make -C projects/adrv9009/zcu102/ clean-all
$ time make -C projects/adrv9009/zcu102/ -j$CORES lib
CORES=1:
real 9m27.223s
user 9m2.556s
sys 0m32.358s
CORES=8:
real 1m54.639s
user 16m26.512s
sys 1m2.317s
i.e. about 5 times faster to build IP core dependencies.
Signed-off-by: Liam Beguin <liambeguin@gmail.com>
Signed-off-by: Jorge Marques <jorge.marques@analog.com>
Replaces Symbolator with custom component diagram generator for more
reliable diagrams.
It uses the IP-XACT file, if it is not found, a placeholder is added
instead.
Signed-off-by: Jorge Marques <jorge.marques@analog.com>
Import aiohttp and asyncio only when needed.
Better warning for unknown signals, params.
Use pattern matching in regmap parsing.
Fixup bundle count.
Add lists clarification to guidelines.
Enforce #1229 rules.
Clean-up Makefile.
Use non-breaking hyphen.
Signed-off-by: Jorge Marques <jorge.marques@analog.com>
1. Simplify the control logic by adding a state machine.
The improvements are on code readability and reliability.
2.Add a flush feature which can be used to clean the data from the DMA fifo.
This is useful when the DMA is programmed in cyclic mode and
data transmission is stopped by dma_transfer_suspend flag
The software intervention is reduced at setting the flag(dma_flush_en).
Flushing can also be done when activating the raw value with dma_flush_en active.
3. Add raw value support. Through this changes a user can set
the dac output to a fixed predefined value in the following two cases:
1. direct, without using the dma.
2. with dma, as a hold value. The fixed value will be kipped after a cyclic
buffer is stopped by axi_dac_interpolate, through dma_transfer_suspend
register/signal.
The raw value ca be set and transmitted independently on each channel.
The predefined value is stored in reg 0x19(0x64). For more details se
the documentation available at
https://wiki.analog.com/resources/fpga/docs/axi_dac_interpolate
axi_dac_interpolate - Remove last sample hold control
axi_ad9963 - Remove last sample hold control and set as default the
last sample hold functionality plus code optimization changes.
Alin-Tudor Sferle
Jorge Marques
Sergiu Arpadi
LBFFilho
PIoandan
StancaPop
Iulia Moldovan
AndrDragomir
laurent-19
IstvanZsSzekely
Jorge Marques
AndreiGrozav
caosjr
Liam Beguin
cristianmihaipopa
Ionut Podgoreanu