5 Commits (aac47463986e3e57a0d6788c519abdd366357228)

Author	SHA1	Message	Date
Laszlo Nagy	0261eade0c	zynq:all: fix SPI clock constraint ... According to data sheets the EMIO SPI controller maximum frequency is just 25MHz. Constrain the SPI clock accordingly.	2019-08-09 16:39:56 +03:00
Laszlo Nagy	5986e87a1f	zynq/zynqmp: create a 50MHz clock on the SPI clock outputs of the PS	2019-05-30 14:55:11 +03:00
Laszlo Nagy	bcba21da71	zcu102: updated IOSTANDARD of Bank 44 IOs to match VCCO 3.3V	2018-06-05 08:52:50 +01:00
Rejeesh Kutty	f3f5353944	zcu102- updates	2016-05-10 15:40:41 -04:00
Rejeesh Kutty	e8fbdd0f5d	zcu102: zynq ultrascale	2016-05-10 15:40:41 -04:00