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11 Commits (aac47463986e3e57a0d6788c519abdd366357228)

Author SHA1 Message Date
Stanca Pop a06c74edc7 fmcjesdadc1: Change rx_div_clk to 125MHz 2019-11-20 10:50:18 +02:00
AndreiGrozav 502989c25f jesd_rst_gen:constraints: Remove invalid false path definitions 
The constraint where added to remove timing problems on the reset path.

The constraint paths do not match anymore. The resets are used in a synchronous
way so we don't need the timing exceptions anyway.

Projects affected by this change:
  - daq3
  - adrv9739
  - ad6676evb
  - fmcadc5
  - daq2/kcu105
  - fmcadc2
  - adrv9371x
  - fmcomms11/zc706
  - fmcjesdadc1
 2018-04-11 15:09:54 +03:00
Istvan Csomortani ac2e5a9dac constraints: Update constraints 
Xilinx recommends that all synchronizer flip-flops have
their ASYNC_REG property set to true in order to preserve the
synchronizer cells through any logic optimization during synthesis
and implementation.
 2017-02-24 13:43:32 +02:00
Rejeesh Kutty 35f660fe06 fmcjesdadc1/vc707- constraint clean-up 2017-02-02 15:05:49 -05:00
Istvan Csomortani 1156aeac16 ad_sysref_gen: Update SYSREF related constraints 2016-12-19 18:07:05 +02:00
Istvan Csomortani 8d799d0316 fmcjesdadc1: Intergrate ad_sysref_gen into project 2016-12-19 13:37:29 +00:00
Istvan Csomortani a54092c9bb fmcjesdadc1: Update projects to xcvr framework 
This commit contains modifications for Xilinx only
 2016-11-10 10:59:52 +02:00
Adrian Costina 59fbd99fdb fmcjesdadc1: Added clock constraint for the ADC path 2016-01-22 15:46:20 +02:00
Adrian Costina 7f9c526683 fmcjesdadc1: VC707 update project 2015-09-24 19:50:14 +03:00
Adrian Costina 11379939d0 fmcjesdadc1: VC707, Updated project to the latest framework 2015-03-30 18:08:19 +03:00
Istvan Csomortani 2ce7695bf7 fmcjesdadc1: Initial commit of VC707 version 2014-09-01 18:47:01 +03:00