a78c95d8fb
adrv9009_zu11eg_som: Add SPI clock constraint
2019-08-01 18:15:45 +03:00
14a4acfd0e
projects/scripts: Fix a typo in adi_env.tcl
2019-07-25 17:58:36 +03:00
fa610d36c6
ad_ghdl_dir: Fix global variable name
...
In #PR318 the global variable $ad_phdl_dir name were changed to
$ad_ghdl_dir.
2019-07-23 10:29:37 +01:00
6655829bc7
daq2: VC707: Remove project
2019-07-22 13:25:46 +01:00
a6cff0f804
motcon2_fmc: Remove project
2019-07-22 13:23:43 +01:00
6a721c0bf0
adi_env: Update system level environment variable definition
...
Our internal repository was changed from phdl to ghdl. Update the
adi_env.tcl scripts and other scripts, which depends on the $ad_ghdl_dir
variable. This way the tools will see all the internal IPs too.
2019-07-22 11:00:45 +03:00
ce5aadb3e4
adrv9361z7035/common/ccbox_constr.xdc: Cosmetics only
2019-07-17 10:37:30 +03:00
6f627c2105
adrv9361z7035/ccbox: Keep by default in powerdown the 12V PS
...
Because of build hazards, the power supply can be randomly powered on,
when the pin is left in high impedance.
2019-07-17 10:37:30 +03:00
5f1cb18c9b
ad7616_sdz/zc706: Fix Build
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- Fix typo
- Remove the unused(old flow) ps interupts
2019-07-10 12:51:42 +03:00
e1d9a36ae0
scripts/adi_project_intel: Rename ALT_NIOS_MMU_ENABLED to NIOS_MMU_ENABLED
2019-06-29 06:53:51 +03:00
04ce10a570
cosmetics: Change Altera to Intel in comments
2019-06-29 06:53:51 +03:00
b0fbe1bb57
util_clkdiv: Seperate the IP source into an intel and xilinx version
2019-06-29 06:53:51 +03:00
5329458a62
library/scripts: Rename adi_ip_alt.tcl to adi_ip_intel.tcl
2019-06-29 06:53:51 +03:00
363494ab9c
library/scripts: Rename adi_ip.tcl to adi_ip_xilinx.tcl
2019-06-29 06:53:51 +03:00
6e6f1347d7
project/scripts: Rename adi_project_alt.tcl to adi_project_intel.tcl
2019-06-29 06:53:51 +03:00
a589753d92
project/scripts: Rename adi_project.tcl to adi_project_xilinx.tcl
2019-06-29 06:53:51 +03:00
43725429ac
adi_project: Rename the process adi_project_xilinx to adi_project
2019-06-29 06:53:51 +03:00
ec67a381e4
adi_project: Rename the process adi_project_altera to adi_project
2019-06-29 06:53:51 +03:00
79b6ba29ce
all: Rename altera to intel
2019-06-29 06:53:51 +03:00
ba4a915af0
ad40xx/zed: fixed system_bd
...
spi_engine_execution: fixed sdo default
2019-06-28 11:18:29 +03:00
cf9d0814d5
ad40xx/zed: Place all the SPI registers near IOB
2019-06-28 11:18:29 +03:00
10e1abc22f
ad40xx_fmc/zed: Delete IOB TRUE constraints
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Vivado can not apply the IOB TRUE constraint to only one bit of a
registers. So these constraints will generate several CRITICAL WARNING.
Taking into consideration the maximum used frequencies and current
architecture these constraints are not critical.
2019-06-28 11:18:29 +03:00
6b110b6fb8
ad5758_sdz/zed: system constraint file cleanup
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removed redundant PACKAGE_PIN properties
2019-06-28 11:18:29 +03:00
0f2a1e7602
ad5758_sdz: Initial commit
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Initial version of AD5758 SDZ evaluation board support on ZedBoard.
No critical warnings in the Vivado log.
Bitstream generation passing.
Bring-up on actual board not done.
2019-06-28 11:18:29 +03:00
9ab88f1200
ad40xx: Initial commit
2019-06-28 11:18:29 +03:00
b46a28d42f
adum7701: Delete redundant interrupt port in system_top
2019-06-28 11:18:29 +03:00
6668accc96
ad7405 : Initial commit
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This project is an inital version of the ADuM7701 (CMOS) or AD7405 (LVDS)
reference board.
2019-06-28 11:18:29 +03:00
554feaa1af
util_pulse_gen: Update ports for all outdated instance
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The new version of util_pulse_gen has different ports and port names.
Update all the instance:
- AD738x_FMC
- AD7768EVB
- ADAQ7980_SDZ
2019-06-28 11:18:29 +03:00
7fa620d253
gtm_projects: Update system_top
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In the latest system_top file we are not bringing out all the interrupt
signals from the block design. Delete all interrupt ports from the
system_wrapper instance.
Following projects were changed:
- AD5766_SDZ
- AD7134_FMC
- AD7616_SDZ
- AD77681EVB
- AD7768EVB
- ADAQ7980
2019-06-28 11:18:29 +03:00
21ce53f765
Revert "Move GTM projects to gtm_projects branch"
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This reverts commit 171093eca4
2019-06-28 11:18:29 +03:00
f22f448d4b
daq3:vcu118: Delete constraint related to smart connect
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Apparently this constraint will cause more harm than good. The tool will
try to prevent an invalid hold violation by increasing the net delay,
causing a setup violation on the same path. (inside the smart connect)
See more info here:
https://forums.xilinx.com/t5/AXI-Infrastructure/Smartconnect-and-Synchronous-Clock-Domain-Crossing-Issues/td-p/904824
2019-06-27 13:47:24 +03:00
4896a84c2d
ad9739a_fmc: DMA should use $sys_dma_resetn
2019-06-21 09:54:21 +03:00
e0a010c959
ad9625_fmc: DMA should use $sys_dma_resetn
2019-06-21 09:54:21 +03:00
4812f64cdc
ad9434: Fix axi_ad9434_dma timing closure
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axi_ad9434_dma/m_dest_axi_aresetn should use sys_dma_resetn
2019-06-21 09:54:21 +03:00
0a3a99bf83
m2k: Define SPI clock constraint
2019-06-21 09:53:14 +03:00
0bbe501764
adrv9009_zu11eg_som: added axi_fan_control
2019-06-14 17:08:38 +03:00
c159909823
adrv9009_zu11eg_som: added i2s
2019-06-14 17:08:38 +03:00
9409df6a6f
adrv9009_zu11eg: Initial commit
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Observation and RX should never run at the same time.
Given that there is no FIFO on the RX and OBS paths, they will use the higheste performance HP ports, which are HP1 and HP2
2019-06-14 17:08:38 +03:00
95afc461a6
fmcomms5: DMA should use $sys_dma_resetn
2019-06-13 10:59:43 +03:00
2e05b70d94
fmcomms11: DMA should use $sys_dma_resetn
2019-06-13 10:59:43 +03:00
dafc97f43a
fmcjesdadc1: DMA should use $sys_dma_resetn
2019-06-13 10:59:43 +03:00
424abe0c02
adrv9009: DMA should use $sys_dma_resetn
2019-06-13 10:59:43 +03:00
5266d2ae88
ad6676evb: DMA should use $sys_dma_resetn
2019-06-13 10:59:43 +03:00
44a9331471
fmcomms2:fmcomms5: ZCU102 uses 500MHz IO delay clock
2019-06-11 18:13:06 +03:00
993497438b
adi_project:adi_project_run: Check if $num_reg exist
2019-06-11 18:13:06 +03:00
896ea4925d
adi_board: Fix ad_mem_hpx_interconnect proc
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Make the lsearch command more robust.
2019-06-11 18:13:06 +03:00
019390f9bf
block_design: Updates with new reset net variables
2019-06-11 18:13:06 +03:00
0e750bea42
adrv9009: Fix dma_clk tree
2019-06-11 18:13:06 +03:00
9072779e41
adrv9371x: Clean out system_db.tcl
2019-06-11 18:13:06 +03:00
de510b45ab
base: Add system_processor_rst for all the global clocks
2019-06-11 18:13:06 +03:00
Adrian Costina
István Csomortáni
Istvan Csomortani
AndreiGrozav
Sergiu Arpadi
Laszlo Nagy