3241924d14
sysid_intel: Added sysid to intel projects
2020-09-11 15:46:06 +03:00
8818089015
a10soc: Reconfiguration interface address width improvement
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The reconfiguration interface's address width is different in various
architectures. Define the required address width in system_qsys.tcl.
2020-09-09 14:15:37 +03:00
9043f3737b
Revert "a10gx: Optimise the base design"
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This reverts commit 9afc871b70
2020-08-11 10:14:18 +03:00
4af0c98c56
a10gx: Fix exceptionSlave interface definition for HPS
2020-08-11 10:14:18 +03:00
0b51c474a1
a10gx: Add a Avalon Pipeline Bridge between EMIF and DMA's
2020-08-11 10:14:18 +03:00
359e5d94ec
a10gx: Remove constraint from eth_ref_clk
2020-08-11 10:14:18 +03:00
9afc871b70
a10gx: Optimise the base design
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Add a clock crossing bridge for the interfaces that runs on a different
clock than the emif_user_clk.
This way we can simplify the main interconnect, and prevent occasional
timing violations.
2019-06-04 11:28:37 +03:00
d690a614c1
a10gx: Force all used tiles to high speed, in order to improve timing
2017-10-04 16:16:00 +01:00
ee01ea3736
daq2/a10gx: Add cfi_flash to qsys
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+ Add cfi_flash to qsys
+ Set nios reset vector to cfi_flash
2017-10-04 11:30:29 +01:00
3a47567f9c
common/a10gx: Chance SPI frequency from 128KHz to 10 MHz
2017-09-19 18:01:18 +03:00
d7e87a60a9
Remove executable flag from non-executable files
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All of these files are source code and are not executable standalone.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-07-28 17:56:07 +02:00
5a98e727f2
A10GX: Update DDR3 configuration
2017-07-27 12:38:14 +01:00
0bd22e78d9
altera- adi-project-create version
2017-06-05 15:24:35 -04:00
cfcb269d38
a10gx- change ddr to 1G
2017-05-15 09:32:36 -04:00
ebeebdddf0
altera- infer latest versions
2017-05-12 13:40:14 -04:00
c728299e71
altera- default to latest version
2017-05-12 13:25:17 -04:00
b3f06af77a
altera srf files do not work
2017-03-22 09:25:50 -04:00
2e22ce3b62
a10gx- ignore preliminary timing model warnings
2017-03-21 10:52:28 -04:00
c1be17a3af
Altera a10 devices: disable warnings regarding unused channels
2017-03-01 11:32:17 +02:00
50552ce7d6
adrv9371x- altera updates
2016-10-27 09:25:00 -04:00
0d095f5da9
a10gx: Added system_type variable in common design
2016-09-08 11:29:14 +03:00
917da79da1
altera- source defaults for qsys-script
2016-08-30 11:50:36 -04:00
c6f4def93d
altera- make mmu a make switch
2016-08-08 11:54:51 -04:00
52ae3ddd6c
a10gx: Updated common files to 16.0
2016-08-01 15:08:12 +03:00
c6c3622816
a10gx: Updated common design adding explicit clock frequency and synchronous reset deassertion
2016-06-30 10:59:29 +03:00
625052f46e
daq2/a10gx- qsys updates
2016-06-07 12:28:04 -04:00
d53b06849e
daq2/a10gx- qsys updates
2016-06-07 12:28:04 -04:00
3516ec28b7
daq2/a10gx- qsys updates
2016-06-07 12:28:04 -04:00
39d23032f1
daq2- qsys updates
2016-05-23 10:55:44 -04:00
72151bb1a6
a10gx: Updated base design to include MMU
2016-05-13 18:44:41 +03:00
8b2542b181
daq2/a10gx: 10AX115S3F45E2SGE3 version
2016-04-20 16:01:12 -04:00
679d471d75
Merge branch 'hdl_2016_r1' into dev
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hdl_2016_r1 contains IP core upgrades to Vivado 2015.4.2 and hdmi_tx improvements.
2016-04-19 18:05:50 +03:00
657144d9a7
a10gx: Updated base design and DAQ2 to the new revision of the a10gx board
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- tried using ATX PLL and fPLL for TX transceiver clocks, but could not get them to lock
- CMU PLL works correctly as temporary solution
2016-03-28 13:21:36 +03:00
377461e0d4
Merge branch 'hdl_2015_r2' into dev
2016-02-19 14:15:27 +02:00
ad9ecbbbb6
daq2: Updated a10gx project to quartus 15.1.1
2016-02-05 17:43:05 +02:00
650d426301
a10gx/base: set gpio to 32
2015-12-11 10:14:37 -05:00
f1b6577447
a10gx/base: separate gpio in/out
2015-12-10 16:04:54 -05:00
83399ef6ee
a10gx: Updated common project to work with Linux (enabled MMU)
2015-11-04 13:35:52 +02:00
01c0fdc809
daq2/a10gx- ethernet fix
2015-09-02 14:31:15 -04:00
e760aa424a
daq2/a10gx-- intmem to ddr
2015-08-19 13:26:38 -04:00
8cc3aa0865
ddr- 933/233
2015-08-19 13:26:38 -04:00
08e46c5ff2
a10gx-base: data-master connections
2015-07-21 10:53:54 -04:00
a87b8fbf94
a10gx- base system only
2015-07-20 09:29:30 -04:00
1f7745610e
daq2- ddr updates
2015-07-14 12:46:52 -04:00
d111692608
daq2/a10gx- ddr-ref @133
2015-06-04 10:53:16 -04:00
aa24c442f5
a10gx- no-ddr
2015-06-01 11:00:01 -04:00
a6cae6b477
iobuf: do is a system verilog keyword
2015-05-21 14:06:17 -04:00
b311b9dac6
a10gx- updates
2015-05-14 14:35:42 -04:00
515dfd88d4
a10gx- added
2015-05-11 11:56:22 -04:00
Sergiu Arpadi
Istvan Csomortani
Adrian Costina
STEVE KRAVATSKY
AndreiGrozav
Lars-Peter Clausen
Rejeesh Kutty