Commit Graph

3529 Commits (ae0f4672b24c0f4ab06c560a97abb972ba3f6d49)

Author SHA1 Message Date
Rejeesh Kutty 3586397f57 altera/common- add asymmetric fifo 2017-03-01 15:35:04 -05:00
Rejeesh Kutty bc6a09c828 adrv9371x/a10soc- dacfifo added 2017-03-01 15:35:04 -05:00
AndreiGrozav 5b5c0dde99 ad6676evb: Set default xcvr parameters to common design 2017-03-01 11:32:17 +02:00
AndreiGrozav b78e9d8c27 daq2_a10gx: Set XCVR Tx/RX clk/data voltage levels at 1V 2017-03-01 11:32:17 +02:00
AndreiGrozav 0cc5130c9a adrv9371x: Set XCVR Tx/RX clk/data voltage levels at 1V 2017-03-01 11:32:17 +02:00
AndreiGrozav c1be17a3af Altera a10 devices: disable warnings regarding unused channels 2017-03-01 11:32:17 +02:00
AndreiGrozav dc168f41fe adrv9371_a10soc: Fixed port assignments 2017-03-01 11:32:17 +02:00
Rejeesh Kutty aad41039bd a10soc- plddr4 settings 2017-02-28 13:36:28 -05:00
Rejeesh Kutty 9c65166e26 ad9371- missing net declarations 2017-02-28 13:31:23 -05:00
Rejeesh Kutty 104e9dfcdc adc/dac-fifo altera cores 2017-02-28 13:30:50 -05:00
Adrian Costina 59dda01419 m2k: Disabled DDS cores for the generic project 2017-02-28 10:10:28 +02:00
Rejeesh Kutty 0d231935ef library/util_dacfifo- match bypass port with axi_dacfifo 2017-02-27 16:06:39 -05:00
Rejeesh Kutty fb4a583613 projects/system_bd- adc/dac fifo board designs 2017-02-27 16:06:39 -05:00
Rejeesh Kutty 6b1a8852a9 dacfifo- bypass port name change 2017-02-27 16:06:39 -05:00
Rejeesh Kutty 19c7b5d340 fmcadc5- move adc fifo settings to system-board 2017-02-27 16:06:39 -05:00
Rejeesh Kutty c1aac4a9fb common: adc/dac fifo board designs 2017-02-27 16:06:39 -05:00
Istvan Csomortani 1d6ddacfd6 axi_ip_constr: Fix constraints
The filter for CDC registers were too generic, and a few non-CDC
register were set as asynchronous register.
2017-02-27 16:25:09 +02:00
Adrian Costina 1c8e63cb68 axi_adc_trigger: Added triggered register 2017-02-27 14:26:19 +02:00
Adrian Costina 37a1c98c12 axi_logic_analyzer: Switched from BUFGMUX to BUFGMUX_CTRL for glitch free clock switching 2017-02-27 14:19:54 +02:00
Adrian Costina 545e458997 m2k: Standalone, ignored critical warning for contraints that should only be applied at the implementation stage 2017-02-27 14:17:29 +02:00
Adrian Costina eda585f0e4 m2k: Connected data[0] and trigger[0] pins to the logic analyzer clock generator input 2 2017-02-27 14:16:32 +02:00
Adrian Costina 908da60ab6 m2k: zed, changed constraints so they are the same with the ZED default configuration
- the voltage can be physically changed between 1.8V, 2.5V and 3.3V
2017-02-27 14:13:34 +02:00
Istvan Csomortani 0059c907ea adrv9371: Drive the TX DMA interface with sys_dma_clk 2017-02-24 15:50:12 +02:00
Istvan Csomortani 11623e79be axi_dacfifo: Fix clock for read address generation 2017-02-24 15:47:04 +02:00
Istvan Csomortani 3e596347fd axi_dacfifo: Delete unused wires 2017-02-24 15:45:51 +02:00
Istvan Csomortani ac2e5a9dac constraints: Update constraints
Xilinx recommends that all synchronizer flip-flops have
their ASYNC_REG property set to true in order to preserve the
synchronizer cells through any logic optimization during synthesis
and implementation.
2017-02-24 13:43:32 +02:00
Istvan Csomortani f326c03ff3 axi_dacfifo: Define constraint for bypass
The bypass module currently is supported, when the DMA data width
is equal with the DAC data width.
The dac_data output is enabled with dac_valid.
2017-02-24 12:35:42 +02:00
Istvan Csomortani b9d3039568 axi_dacfifo: Register the dac_valid signals 2017-02-24 12:34:58 +02:00
Istvan Csomortani debc6e2066 axi_dacfifo: Data from DMA is validated with dma_ready too 2017-02-24 12:32:25 +02:00
Istvan Csomortani dfcd5214a0 axi_dacfifo: axi_dvalid should come from dacfifo_rd module 2017-02-24 12:28:46 +02:00
Istvan Csomortani 6b90054343 axi_ad9361: Define CDC constraint for tdd_sync 2017-02-24 11:24:07 +02:00
Istvan Csomortani 1fce57f6c3 axi_dacfifo: Redesign the bypass functionality 2017-02-23 17:32:31 +02:00
Adrian Costina 573959c826 Makefiles: fixed axi_adxcvr/util_adxcvr Makefiles to include interfaces dependancy 2017-02-23 16:16:34 +02:00
Istvan Csomortani d820d3d245 util_sync_constr: Preserve 1bit CDCs with ASYNC_REG true 2017-02-23 11:44:01 +02:00
Istvan Csomortani 94bda1d415 axi_ad9361: Preserve 1bit CDCs with ASYNC_REG true 2017-02-23 11:43:10 +02:00
Istvan Csomortani 2da7dd4079 axi_ip_constr: Update constraints
Xilinx recommends that all synchronizer flip-flops have
their ASYNC_REG property set to true in order to preserve the
synchronizer cells through any logic optimization during synthesis
and implementation.
2017-02-23 11:33:25 +02:00
Istvan Csomortani 2b354af876 axi_ad9361_tdd: Register the tdd_sync_cntr output 2017-02-23 11:31:23 +02:00
Rejeesh Kutty c598e84258 remove processing order (no clock def dependency) 2017-02-22 16:02:08 -05:00
Rejeesh Kutty edd5e9570f file renamed; sed output; fingers crossed 2017-02-22 15:56:37 -05:00
Rejeesh Kutty b00dc4b195 plddr3- change to board files 2017-02-22 15:22:50 -05:00
Rejeesh Kutty 89b49d2f67 fifo- as board files 2017-02-22 15:18:50 -05:00
Rejeesh Kutty 879ed64bb6 compression flag changes 2017-02-22 15:15:53 -05:00
Rejeesh Kutty 8a5e2ff46e sys_wfifo- removed 2017-02-22 15:13:18 -05:00
Rejeesh Kutty 754ac6a403 w/r-fifo- removed 2017-02-22 15:10:06 -05:00
Istvan Csomortani e3ac341aad axi_dacfifo: Fix constraints 2017-02-21 14:45:18 +02:00
Adrian Costina 040b61de60 fmcadc5: Updated default parameters 2017-02-20 17:13:58 +02:00
Rejeesh Kutty a15e05c497 adcfifo- remove axi-byte-width parameter 2017-02-17 15:29:10 -05:00
Rejeesh Kutty cb3d1883bc fmcjesdadc1/a5gt- hard placement of ddr hr/qr registers 2017-02-17 15:21:33 -05:00
Istvan Csomortani 981a61bf16 axi_dacfifo: Clean up the axi_dacfifo_wr.v module 2017-02-17 18:40:02 +02:00
Adrian Costina e8bcbb74da scripts: fixed tcl syntax for altera projects not meeting timing 2017-02-16 21:21:51 +02:00