Commit Graph

8 Commits (ae7ec823349f60c1d8a5ddb8f39dfb89527fc531)

Author SHA1 Message Date
Adrian Costina 9093a8c428 library: Move ad_iobuf to the common library, as it's not Xilinx specific
Updated all system_project and Makefiles
2020-11-02 16:13:35 +02:00
Sergiu Arpadi d8ab27b2af sysid: Remove cstring init string 2020-09-30 19:12:24 +03:00
Adrian Costina c4b94fc564 adrv9009zu11eg: Add S JESD204 parameter for the projects 2020-02-18 11:19:02 +02:00
Adrian Costina 645696e5b4 adrv9009zu11eg: Extend SPI connection to the PL HD PINS expansion 2020-02-18 11:19:02 +02:00
Adrian Costina 09ad67bfd7 adrv9009zu11eg: Make the project more parametrizable 2019-12-04 14:59:18 +02:00
Adrian Costina 0cb5c0bdaf adv9009zu11eg: Update FPGA to -2. Update DDR4 clock frequency 2019-11-27 16:27:44 +02:00
Adrian Costina dfe3258a4f adrv9009zu11eg: Add axi_sysid 2019-11-19 10:29:57 +02:00
Adrian Costina a589a2c7eb adrv9009_zu11eg_som: Change design partitioning
Create a structure similar with ADRV936x projects
2019-11-14 15:25:23 +02:00