09bcecb6ed
m2k: Simplify DMA connection to HP1
2017-03-15 15:11:30 +02:00
2a9b3cea09
m2k: Changed the way DMAs connect to the PS7 DDR, to optimize resources use
2017-03-14 13:57:50 +02:00
f7c2bd943b
m2k: Enable AD9963 adc data path processing.
...
- part of the path is the sign extension module. Without it, the triggering doesn't work correctly
2017-03-13 23:18:29 +02:00
c3c8c366d3
axi_ad9361- add receive init delay
2017-03-13 16:28:53 -04:00
dac75f79ab
fmcomms5/usrpe31x- add iodelay report
2017-03-10 13:38:27 -05:00
1b3f752c3d
pzsdr1/pzsdr2/pluto- add iodelay report
2017-03-10 12:55:22 -05:00
0ae79ca7ac
move/rename - delay script belongs to ad9361
2017-03-10 12:44:32 -05:00
e736504e0f
fmcjesdadc1, usdrx1: Using the same clock in rx_data path
2017-03-10 14:26:51 +02:00
d08d1d5a1b
adrv9371x ,daq3, fmcomms7, fmcomms11: add dac_fifo missing reset connection
2017-03-10 14:20:42 +02:00
452e5e5ce0
fmcomms2- add delay reporting for iodelay
2017-03-09 15:29:15 -05:00
8bdfbe2b0a
fmcomms2- report delays
2017-03-09 15:21:42 -05:00
7e5d8664ad
fmcjesdadc1_a5gt: rx_data pins are all associated to the same clock
2017-03-09 08:57:03 +02:00
0e002f2f31
daq3_a10gx: Set XCVR Tx/RX clk/data voltage levels at 1V
2017-03-09 08:50:55 +02:00
191669ad28
daq2_common: Fix the dac_rst for DAC FIFO
2017-03-07 16:13:46 +02:00
fc8af6903f
pzsdr2/ccfmc- add rf input protection
2017-03-06 16:19:55 -05:00
3fa9a30f0e
a10soc/plddr4- lower mem clk to meet timing
2017-03-06 14:12:25 -05:00
38a27d02f6
a10soc/plddr4- differential refclk
2017-03-06 14:11:36 -05:00
936c441763
adrv9371x- dacfifo bypass-gpio control
2017-03-06 10:35:09 -05:00
762276a880
adrv9371x- dacfifo changes
2017-03-06 10:33:52 -05:00
4a6fe54fcf
daq2_common: Update common scripts
...
Add new port connection for util_dacfifo
2017-03-03 18:49:10 +02:00
ec89b1a45f
altera/adrv9371x- add dacfifo
2017-03-01 15:52:07 -05:00
bc6a09c828
adrv9371x/a10soc- dacfifo added
2017-03-01 15:35:04 -05:00
5b5c0dde99
ad6676evb: Set default xcvr parameters to common design
2017-03-01 11:32:17 +02:00
b78e9d8c27
daq2_a10gx: Set XCVR Tx/RX clk/data voltage levels at 1V
2017-03-01 11:32:17 +02:00
0cc5130c9a
adrv9371x: Set XCVR Tx/RX clk/data voltage levels at 1V
2017-03-01 11:32:17 +02:00
c1be17a3af
Altera a10 devices: disable warnings regarding unused channels
2017-03-01 11:32:17 +02:00
dc168f41fe
adrv9371_a10soc: Fixed port assignments
2017-03-01 11:32:17 +02:00
aad41039bd
a10soc- plddr4 settings
2017-02-28 13:36:28 -05:00
59dda01419
m2k: Disabled DDS cores for the generic project
2017-02-28 10:10:28 +02:00
fb4a583613
projects/system_bd- adc/dac fifo board designs
2017-02-27 16:06:39 -05:00
6b1a8852a9
dacfifo- bypass port name change
2017-02-27 16:06:39 -05:00
19c7b5d340
fmcadc5- move adc fifo settings to system-board
2017-02-27 16:06:39 -05:00
c1aac4a9fb
common: adc/dac fifo board designs
2017-02-27 16:06:39 -05:00
545e458997
m2k: Standalone, ignored critical warning for contraints that should only be applied at the implementation stage
2017-02-27 14:17:29 +02:00
eda585f0e4
m2k: Connected data[0] and trigger[0] pins to the logic analyzer clock generator input 2
2017-02-27 14:16:32 +02:00
908da60ab6
m2k: zed, changed constraints so they are the same with the ZED default configuration
...
- the voltage can be physically changed between 1.8V, 2.5V and 3.3V
2017-02-27 14:13:34 +02:00
0059c907ea
adrv9371: Drive the TX DMA interface with sys_dma_clk
2017-02-24 15:50:12 +02:00
ac2e5a9dac
constraints: Update constraints
...
Xilinx recommends that all synchronizer flip-flops have
their ASYNC_REG property set to true in order to preserve the
synchronizer cells through any logic optimization during synthesis
and implementation.
2017-02-24 13:43:32 +02:00
1fce57f6c3
axi_dacfifo: Redesign the bypass functionality
2017-02-23 17:32:31 +02:00
c598e84258
remove processing order (no clock def dependency)
2017-02-22 16:02:08 -05:00
edd5e9570f
file renamed; sed output; fingers crossed
2017-02-22 15:56:37 -05:00
b00dc4b195
plddr3- change to board files
2017-02-22 15:22:50 -05:00
89b49d2f67
fifo- as board files
2017-02-22 15:18:50 -05:00
879ed64bb6
compression flag changes
2017-02-22 15:15:53 -05:00
8a5e2ff46e
sys_wfifo- removed
2017-02-22 15:13:18 -05:00
754ac6a403
w/r-fifo- removed
2017-02-22 15:10:06 -05:00
040b61de60
fmcadc5: Updated default parameters
2017-02-20 17:13:58 +02:00
a15e05c497
adcfifo- remove axi-byte-width parameter
2017-02-17 15:29:10 -05:00
cb3d1883bc
fmcjesdadc1/a5gt- hard placement of ddr hr/qr registers
2017-02-17 15:21:33 -05:00
e8bcbb74da
scripts: fixed tcl syntax for altera projects not meeting timing
2017-02-16 21:21:51 +02:00
95a4ea20c8
axi_dacfifo: Delete redundant parameter BYPASS_EN
2017-02-16 19:53:44 +02:00
8453d758c2
scripts: If an altera project doesn't meet timing, rename the sof
2017-02-16 19:20:49 +02:00
343d0472d4
fmcadc2: Move GT setting to common/system_bd.tcl
2017-02-16 14:56:25 +02:00
07184b31d2
fmcadc2: Define default clock selection for Xilinx GTs
2017-02-16 12:35:24 +02:00
86c279c238
pzsdr1: ccbox, moved I2S core to DMA0 and DMA1 to fix critical warnings
2017-02-14 14:51:49 +02:00
46290193f3
pzsdr2: ccusb, renamed clk_out to clkout_in
2017-02-14 11:58:11 +02:00
27119343f2
pzsdr2: ccusb, connect unused clock pins to GND
2017-02-14 11:56:54 +02:00
fa37f4dd0a
pzsdr2: Don't set a disabled parameter
2017-02-14 11:56:08 +02:00
6a9b7580de
pzsdr1: ccusb, renamed clk_out to clkout_in
2017-02-14 11:54:46 +02:00
acef0113d1
pzsdr1: ccusb, connect unused clock pins to GND
2017-02-14 11:50:37 +02:00
46883731eb
pzsdr1: Don't set a disabled parameter
2017-02-14 11:50:06 +02:00
a569b6bf0c
pluto: Interpolation, connect fifo_rd_valid to s_axis_data_tvalid
2017-02-13 18:08:52 +02:00
e215a091b2
m2k: standalone, added explicit fclk_clk0 and fclk_clk1 constraints
2017-02-13 12:02:59 +02:00
4e62fb0ef3
m2k: Add reset circuitry on the logic_analyzer clock domain
2017-02-13 12:02:11 +02:00
5fa6dba333
Make: Update Makefiles
2017-02-10 16:32:58 +02:00
f5f1f47691
ad9467_fmc: Delete asynchronous clock group definition
...
This is a very bad way to handle timing. All the false path
should be defined explicitly, rather than define asynchronous clock
domains.
2017-02-10 16:21:35 +02:00
c39ed08edd
zcu102/*- actual clock == desired clock
2017-02-06 12:53:47 -05:00
58872aa3ef
fmcomms2/zc706pr- prcfg is a single clock synchronous design
2017-02-06 10:59:18 -05:00
971bcbb0fc
fmcomms1: Remove project
2017-02-03 16:42:44 +02:00
096274a033
daq2/zcu102- fix refclock pin swap
2017-02-03 09:26:07 -05:00
7c363cd5a7
daq3/a10gx/system_constr.sdc- fix typo
2017-02-03 09:26:07 -05:00
35f660fe06
fmcjesdadc1/vc707- constraint clean-up
2017-02-02 15:05:49 -05:00
d46352928a
fmcomms5- fix ovf net connections
2017-02-02 14:24:06 -05:00
6aadb49e80
m2k: Remove use board flow from the standalone version
2017-02-02 12:58:58 +02:00
0d0c3e99fd
m2k: Added I2C pull-ul, removed SLEW constraints
2017-02-02 12:35:46 +02:00
85ff496c12
daq2/a10gx- gpio match with others
2017-02-01 20:54:56 -05:00
5155b3f46d
m2k: Fix gpio buswidth
2017-02-01 17:43:01 +02:00
cfff70d358
M2K: Update standalone project
...
- configured PS7 similar to pluto. Added specific constraints instead of default PS7
- moved ad9963_resetn and en_power_analog to gpio[0] and gpio[1]
2017-02-01 14:27:11 +02:00
6bdd853b88
m2k: Updated PS7 configuration
2017-01-31 23:08:53 +02:00
b14d740f87
M2K: initial commit
2017-01-31 16:43:40 +02:00
d5af828b9c
Merge branch 'dev' into hdl_2016_r2
2017-01-30 17:10:05 +02:00
97d72d2f65
a10gx- xilinx/altera sync-up
2017-01-30 10:01:28 -05:00
b14e7fe4ee
daq3/kcu105- 1.25GSPS
2017-01-30 10:01:28 -05:00
48ad24cdbe
enable partial reconfiguration mode
2017-01-27 09:26:53 -05:00
be1328c55b
kcu105- added missing ethernet configurations
2017-01-23 10:14:09 -05:00
661413627f
daq3- round about way to avoid ip getting locked
2017-01-20 15:55:33 -05:00
62792ddaed
adrv9371x: Change the axi_adxcvr cores addresses
...
Because the S_AXI interface of the axi_adxcvr core was infered
using the process adi_ip_properties, the interface address range
has changed from 4k to 64k. As a result, all the addresses of
the axi_adxcvr cores were changed and realigned.
2017-01-19 15:23:03 +02:00
ecd152c90d
pzsdr1: ccbrk_cmos, fix clkdiv parameters
2017-01-18 12:04:04 +02:00
165ba76d9d
pzsdr1: Added FIFOs for DAC and ADC paths so that they work at l_clk or l_clk/2
2017-01-18 12:01:24 +02:00
319a883c00
pzsdr2: Added FIFOs for DAC and ADC paths so that they work at l_clk/2 or l_clk/4
2017-01-18 12:00:10 +02:00
9344dd34dc
zcu102: Update project to include clkdiv
2017-01-16 14:47:31 +02:00
4dcad7e116
fmcomms2: zcu102, update clkdiv device parameter
2017-01-16 14:38:37 +02:00
b622b6592e
FMCOMMS5/ZCU102 : Merge from njpillitteri/hdl:dev
...
Pull request Dev #26
2017-01-13 14:47:16 +02:00
d2e7b6b635
fmcomms5: Added FIFOs for DAC and ADC paths so that they work at l_clk/2 or l_clk/4
2017-01-13 14:18:59 +02:00
a36057679a
fmcomms2: Update Makefiles
2017-01-13 14:16:21 +02:00
15c5bc7012
fmcomms2: zcu102, changed clkdiv C_SIM_DEVICE parameter to ultrascale
2017-01-13 13:57:32 +02:00
b84325d43f
fmcomms2: take into consideration both adc_r1 and dac_r1 for clock division selection
2017-01-13 13:56:04 +02:00
f003b5b35a
fmcjesdadc1: Reduce SYSREF period
2017-01-12 16:10:45 +02:00
e77428c50e
fmcomms2: Added FIFOs for DAC and ADC paths so that the path works at l_clk / 2 or l_clk /4
...
- removed ILA
2017-01-11 18:12:35 +02:00
37d54bb984
fmcjesdadc1/a5gt- max delay fit only
2017-01-04 16:04:19 -05:00
8b74e911b8
fmcjesdadc1/a5gt- qr to ddio max delay
2017-01-04 14:10:44 -05:00
e4e5b30ade
fmcadc5: Integrate ad_sysref_gen into the project
2017-01-03 13:52:39 +02:00
14ded4f123
fmcjeadadc1/a5soc- ad_sysref_gen updates
2016-12-22 15:59:45 -05:00
b089173b4c
fmcjesdadc1/a5soc- cpu clock is 50m for a5gt also
2016-12-22 14:14:21 -05:00
aa6c94c993
usdrx1/a5gt: ddr3 use ip constraints
2016-12-22 14:14:21 -05:00
18660c7ab4
fmcjesdadc1/a5gt: ddr3 use ip constraints
2016-12-22 14:14:21 -05:00
2bea337aa2
fmcjesdadc1/a5gt- use 50m-mem-cpu-clk
2016-12-22 14:14:21 -05:00
5d683943ab
fmcjesdadc1/a5gt- remove ad-sysref-gen-pack
2016-12-22 14:14:21 -05:00
f1168f9e29
fmcjesdadc1/a5gt- use xilinx setup 2-dma
2016-12-22 14:14:21 -05:00
1ceec2e2a9
projects/a5gt- use 50m afi clock for cpu- xcvr reconfig timing
2016-12-22 14:14:21 -05:00
eba30b0cde
projects/altera- qii_auto_pack option
2016-12-22 14:14:21 -05:00
4a783d523d
projects/altera* - default & common qsys commands
2016-12-20 16:27:44 -05:00
3e57ff1fc5
z-mpsoc- map 0x4-0x8,0x7-0x9
2016-12-20 16:14:38 -05:00
1156aeac16
ad_sysref_gen: Update SYSREF related constraints
2016-12-19 18:07:05 +02:00
da7f4608a8
fmcjesdadc1/usdrx1: Clean up the mess
...
Delete accidentally commited generated files.
2016-12-19 15:35:20 +00:00
f47863bbcf
usdrx1: Integrate ad_syref_gen into the project
2016-12-19 14:36:01 +00:00
8d799d0316
fmcjesdadc1: Intergrate ad_sysref_gen into project
2016-12-19 13:37:29 +00:00
0c42e04bc3
fmcadc2: Integrate ad_sysref_gen into the project
2016-12-19 12:16:05 +00:00
67390c2a95
ad6676evb: Update projects with ad_sysref_gen
2016-12-19 10:52:25 +00:00
8879218502
a5gte: Fixed timing violations
2016-12-16 15:37:51 +02:00
c0b0f9b7e9
ad6676evb: Connect SYS_REF to GPIO
2016-12-14 17:55:50 +02:00
557efed5d9
ad6676evb: Update clock constraints
2016-12-14 17:55:49 +02:00
3a2c889115
ad6676evb: Update GT configuration
2016-12-14 17:55:49 +02:00
d962614000
usdrx1/zc706: Disabele axi_spi constraint file
...
The interface ports of the AXI SPI IP are not connected
directly to a IOBUF, this results in a CRITICAL WARNING
2016-12-13 19:23:51 +02:00
d5165ca81f
motcon_fmc: Tie unused pins to GND
2016-12-13 19:20:13 +02:00
1515b6f1af
fmcomms7/zc706: Disabele axi_spi constraint file
...
The interface ports of the AXI SPI IP are not connected
directly to a IOBUF, this results in a CRITICAL WARNING
2016-12-13 19:18:18 +02:00
8846141467
fmcomms1/kc705: Disabele axi_spi constraint file
...
The interface ports of the AXI SPI IP are not connected
directly to a IOBUF, this results in a CRITICAL WARNING
2016-12-13 19:16:31 +02:00
c455d2d64f
fmcadc2/vc707: Disabele axi_spi constraint file
...
The interface ports of the AXI SPI IP are not connected
directly to a IOBUF, this results in a CRITICAL WARNING
2016-12-13 19:15:44 +02:00
8ebc8fe4e2
updated makefiles
2016-12-09 23:06:41 +02:00
06aab8ebbd
pzsdr1: Set the device core to 1R1T mode
2016-12-09 16:35:46 +02:00
8e69c838e1
common/ac701: Connect axi_ddr_cntrl/device_temp_i to GND
2016-12-09 13:54:39 +02:00
23c91ca48a
pzsdr1/lvds: The interface runs at max 122.88 MHz
2016-12-09 11:45:11 +02:00
f799c40cf0
usdrx1/a5gt- xcvr interface changes
2016-12-08 16:05:23 -05:00
c114888956
usdrx1- updates
2016-12-08 16:05:23 -05:00
b0eff57b0f
fmcomms2/zc702: Fix critical warnings
2016-12-08 19:54:52 +02:00
3dceb53984
fmcadc2/vc707: Fix timing violations
2016-12-08 19:51:18 +02:00
252c67ceff
fmcomms6: Delete project
...
This project will not be supported in further releases.
2016-12-08 17:22:41 +02:00
fb287d0178
kcu105- updates to match xilinx trd
2016-12-08 09:32:33 -05:00
3bc9df4c51
fmcomms5: Fixed the wornings created by TDD missing connections to axi_ad9361 core
2016-12-07 21:43:19 +02:00
8eaae98728
fmcadc2: Updates
2016-12-07 21:43:19 +02:00
801da3cb25
daq3/kcu105- fix timing violations
2016-12-06 12:31:40 -05:00
2d7fb03b93
adrv9371x/a10gx- fix os xcvr parameters
2016-12-06 12:31:40 -05:00
ad96c5e881
daq3/zc706: Change the speed grade of the FPGA to 3
2016-12-06 15:24:23 +02:00
8f94103f8b
daq1/a10gx: Makefile fix
2016-12-06 15:24:23 +02:00
95ee7c093c
daq1/a10gx: Update system_bd port names
2016-12-06 15:24:23 +02:00
b7143a7a3b
daq1/a10gx: Update IO pin assignments
2016-12-06 15:24:22 +02:00
a415625069
daq1/a10gx: Add spi wrapper file to the project
2016-12-06 15:24:22 +02:00
e30a80fda0
daq1_spi: Delete device specific macro instantiation
2016-12-06 15:24:21 +02:00
7a8dc92b84
usb_fx3: Add interrupt monitor and increase ILA data depth
2016-12-06 11:55:28 +02:00
1e4bdea80c
usrpe31x: Fix Makefile
2016-12-06 11:07:42 +02:00
4b7bf422ee
pzsdr2/ccbox- remove imu intr on pl
2016-12-05 10:21:42 -05:00
351811e13f
pzsdrx/ccbox- imu intr on gpio
2016-12-05 10:18:40 -05:00
170c781d02
hdlmake.pl- updates
2016-12-01 13:52:11 -05:00
6e89ac3d65
pzsdr2: ccusb_lvds, add flag_a,flag_b signals
2016-11-30 17:39:02 +02:00
0faa1ebff2
pzsdr1: ccusb_lvds, add flag_a,flag_b signals
2016-11-30 17:38:04 +02:00
84a76b9dea
imageon: Invert HDMI TX clock
...
The ADV7511 samples the parallel data bus at the rising edge of sample
clock. Generate the clock so that the falling edge is aligned to updating
the bus data. This creates larger timing margins on each side of the
sampling edge and makes the design more robust.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2016-11-29 15:43:24 +01:00
24cc8d284b
imageon: Increase RX DMA FIFO size
...
Increase the RX DMA FIFO to be able to better compensate for momentarily
memory bus contention. This has shown to resolve occasional overflows that
would occur under high system memory load.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2016-11-29 14:12:39 +01:00
99dae73d96
imageon: Connect hdmi_rx_core output clock to DMA
...
Connect the HDMI RX core output clock to the DMA rather than connecting the
HDMI RX input clock directly. This will allow the HDMI RX core to modify
the clock and e.g. insert clock buffers or similar.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2016-11-29 14:12:39 +01:00
07217740b5
imageon: Increase HDMI RX clock constraint
...
The ADV7611 is rated for a maximum clock rate of 165MHz. Increase the clock rate constraint to match this.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2016-11-29 14:12:39 +01:00
284fbac571
usdrx1: Xcvr updates, so that the channel parameters are correctly configured from boot time
2016-11-28 14:16:07 +02:00
45fd4f806d
fmcjesdadc1: Fixed RX_PMA_CFG parameter
2016-11-25 16:33:58 +02:00
11b57290f1
fmcadc5- replaced with axi_adxcvr
2016-11-23 16:22:05 -05:00
22e230618c
scripts/adi_board.tcl- support multiple xcvrs
2016-11-23 16:22:05 -05:00
862bd7ef2c
daq3/zc706- xcvr changes
2016-11-23 15:02:20 -05:00
4e3e623530
pzsdr2/ccpci- updates
2016-11-23 14:02:59 -05:00
e5d3bae54d
projects/ad6676-adrv9371: xcvr updates
2016-11-23 11:06:22 -05:00
daa3df4b96
projects/- xcvr updates
2016-11-22 16:23:05 -05:00
8f562fd069
xcvr updates- board procedure
2016-11-22 14:43:36 -05:00
b1a9bd96f1
daq2: xcvr pll changes
2016-11-22 12:53:29 -05:00
750b23621b
board-tcl: xcvr qpll/cpll changes
2016-11-22 12:53:02 -05:00
4ed7469286
fmcadc4/zc706- updates
2016-11-22 10:32:05 -05:00
8c4279f618
pzsdr1: Added ccusb_lvds initial project
2016-11-22 16:58:34 +02:00
3d0049d274
pzsdr2: ccusb_lvdsr, updated project for the latest schematic
2016-11-22 16:55:52 +02:00
aff45eae5f
fmcadc2: xcvr updates
2016-11-21 18:45:38 +02:00
69ee410d3d
fmcomms2/zc706pr- bypass pr as default
2016-11-21 09:45:10 -05:00
4739d05269
zc706pr/common- removed
2016-11-18 14:52:39 -05:00
f43248c2bc
common/pzsdr*- removed
2016-11-18 11:32:43 -05:00
0d75bcb606
pzsdr2: ccbox: Use DMA interface 0+1 for audio
...
There is a bug in the ps7 component specification that causes critical
warnings to appear in the build log if DMA interface 0 is disabled, but any
other DMA interface is enabled.
Work around this issue by using DMA interface 0 and 1 instead of 1 and 2
for the I2S DMA.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2016-11-18 14:03:46 +01:00
b62f60b0da
pzsdr1/ccbox- updates
2016-11-17 16:14:28 -05:00
935f8a5c7b
pzsdr1/ccbox- constraints
2016-11-17 16:13:53 -05:00
4f65bcb3b2
pzsdr1/ccbrk_cmos- updates
2016-11-17 15:32:49 -05:00
e85dd2740a
pzsdr1/ccbrk_lvds- updates
2016-11-17 15:32:25 -05:00
a61da1d2ac
pzsdr1/common- updates
2016-11-17 15:31:25 -05:00
aa02ca875f
pzsdr1- common files
2016-11-17 13:40:25 -05:00
8c25402d53
pzsdr1- common files
2016-11-17 13:40:04 -05:00
4dae754287
pzsdr1- added readme
2016-11-17 11:29:01 -05:00
778638a7a1
pzsdr2- make updates
2016-11-17 10:26:45 -05:00
74bf4dfb80
pzsdr2- gpio- turn-around
2016-11-17 10:24:50 -05:00
d0166a4c7e
ccbox- updates
2016-11-17 10:24:11 -05:00
c2b7cbd61b
ccbox- constraints
2016-11-17 10:23:51 -05:00
5e6b931150
ccbox- added
2016-11-17 09:28:33 -05:00
fb5d36b250
pzsdr2- update ccfmc
2016-11-16 16:27:41 -05:00
95c44b687e
pzsdr2- fmc/pci constraints
2016-11-16 16:27:41 -05:00
11347c49be
fmcomms11- device set to -3
2016-11-16 13:43:07 -05:00
b85a282748
fmcomms11- lane swap
2016-11-16 10:26:47 -05:00
bdd14c3874
README: Delete second rule under headers
...
By default there is a rule under each header, no need for another one.
2016-11-16 11:04:43 +02:00
81e47edcd5
README: Set links for documentation
2016-11-16 10:57:39 +02:00
fabbe4981e
Update README.md
...
updated
2016-11-15 16:15:55 -05:00
538a1c977f
pzsdr2: make files
2016-11-15 16:00:55 -05:00
4905e80df8
Update README.md
...
updated
2016-11-15 14:16:46 -05:00
db243df97e
pzsdr2- updates
2016-11-15 14:16:06 -05:00
0897716167
fmcadc4: xcvr updates
2016-11-15 16:03:52 +02:00
cac4057449
daq2/common: Altera updates
2016-11-15 16:03:52 +02:00
cfd3ea61f1
pzsdr-to-pzsdr2
2016-11-14 14:12:22 -05:00
f64b44c8ac
sdrstk2pluto- contents
2016-11-11 13:52:57 -05:00
2ececad58c
sdrstk-2-pluto
2016-11-11 13:49:04 -05:00
c80033cb1b
util_fir_int: removed s_axis_data_tvalid and updated sdrstk
2016-11-11 17:52:19 +02:00
e62fe0c086
fmcjesdadc1- a5gt/a5soc- sysclk is different
2016-11-11 10:34:18 -05:00
7008c641b5
axi_adrv9371/zc706: Constraints update
...
From source *jesd_rstgen* is a false path for TX and RX_OS too.
2016-11-11 10:35:09 +02:00
85eac8c811
fmcjesdadc1/a5*- updates
2016-11-10 16:57:06 -05:00
959055bd54
common/a5gt- updates
2016-11-10 16:56:35 -05:00
7a2c713a4e
fmcjesdadc1/a5* - hdlmake.pl
2016-11-10 11:37:06 -05:00
c6730ab2d7
fmcjesdadc1/a5gt- updates
2016-11-10 11:36:41 -05:00
c207589f4b
fmcjesdadc1/a5gt - qsys2tcl flow
2016-11-10 11:32:29 -05:00
8af0731bb0
a5gt- qsys2tcl flow
2016-11-10 11:30:18 -05:00
7a606cbae1
sdrstk: Maximum clock frequency is 61.44 in CMOS mode
2016-11-10 17:45:35 +02:00
d29ef14f36
sdrstk: Configured ad9361 in 1r1t mode
2016-11-10 17:06:42 +02:00
a54092c9bb
fmcjesdadc1: Update projects to xcvr framework
...
This commit contains modifications for Xilinx only
2016-11-10 10:59:52 +02:00
d6918de19e
ad6676: Update projects to xcvr frame work
2016-11-10 10:39:46 +02:00
3cc416ca60
pzsdr1- fix typo on system_ps7
2016-11-09 12:04:30 -05:00
35c2dd5d6d
adrv9371x/zc706: Fix constraints
2016-11-09 16:34:08 +02:00
0b58a2a1db
avl_adxcvr- sysclk frequency
2016-11-09 09:21:07 -05:00
aef3e87d7e
fmcjesdadc1/a5soc -- xcvr frame work updates
2016-11-08 15:20:48 -05:00
53c2f0642b
fmcjesdadc1/a5soc -- xcvr frame work updates
2016-11-08 15:20:33 -05:00
f0af8216ce
common/a5soc- device can not run at 100M cpu clock
2016-11-08 15:19:23 -05:00
d9cfccc05f
common/a5soc- gpio in/out separation
2016-11-08 15:19:02 -05:00
acb9bf3902
hdlmake- a5soc/a5gt- updates
2016-11-04 15:02:57 -04:00
6b492b79db
a10soc - remove default assignments
2016-11-04 15:01:19 -04:00
8ea9beffaf
fmcjesdadc1- a5soc tcl updates
2016-11-04 15:01:19 -04:00
4e99c3be9a
a5soc- tcl flow updates
2016-11-04 15:01:19 -04:00
ce3b6a2d3f
adrv9371x: Updated constraints for altera projects
2016-11-04 18:20:46 +02:00
0dfbb0af11
arradio/c5soc- constraints changes- interface 1r1t
2016-11-03 11:25:52 -04:00
128ca7719a
ccpci_lvds- rev.d. xcvr pin changes
2016-11-02 16:41:04 -04:00
1cbea90bac
altera - a10gx bank swap
2016-11-01 12:41:25 -04:00
1e0fed82f7
alt_serdes- a10 ddio fixes
2016-11-01 12:41:25 -04:00
671a547c2b
hdlmake- updates
2016-11-01 12:41:25 -04:00
d010f3e687
sdrstk: Update Makefile to remove pack/cpack dependancy and add util_fir_dec/util_fir_int dependancy
2016-10-28 16:13:52 +03:00
ac8a6124af
sdrstk: Added interpolation and decimation filters. Removed cpack/upack
2016-10-27 19:33:28 +03:00
50552ce7d6
adrv9371x- altera updates
2016-10-27 09:25:00 -04:00
f752f0c9d7
a10soc- xcvr updates
2016-10-27 09:25:00 -04:00
d4c7b7ca57
ccusb_lvds: Fixed IIC constraints
2016-10-26 11:12:02 +03:00
6607aa707d
pzsdr1: Renamed projects to have lvds/cmos sufix
2016-10-26 11:09:43 +03:00
9ff92fdf5b
pzsdr: Renamed projects to have lvds/cmos sufix
2016-10-26 11:07:29 +03:00
b8363d778d
arradio: Makefile update
2016-10-25 20:36:56 +03:00
138eeebc9b
ccusb_lvds: Initial commit
2016-10-25 16:32:44 +03:00
5731ba3300
fmcomms11- xcvr updates
2016-10-24 09:51:40 -04:00
7e57a89ce5
daq1: Add support for A10GX
2016-10-24 11:43:33 +03:00
c9ac870086
usrpe31x- updates
2016-10-21 13:59:43 -04:00
7b958fed87
hdlmake- updates
2016-10-21 13:59:43 -04:00
48e90f0e9b
usrpe31x- added
2016-10-21 13:59:43 -04:00
801f980aeb
adrv9371: Fix parameter name
2016-10-21 12:50:20 +03:00
3abd87631a
fmcomms11: Fix parameter name
2016-10-21 12:49:48 +03:00
7db0c03a92
pzsdr1+ccbox -- updates
2016-10-19 10:32:28 -04:00
c1b7c5e77a
usb_fx3: Added FIFO on the FX3 to Zynq path, between FX3 core and DMA core
2016-10-19 09:30:51 +03:00
17cfdd6be9
fmcomms2/a10gx: Update Makefile and qsys script
2016-10-18 12:42:14 +03:00
918ce45e2a
pzsdr1/ccbox- updates
2016-10-17 16:29:57 -04:00
cb97bc500a
hdlmake updates
2016-10-17 16:29:57 -04:00
950acaed15
ccbox- copy
2016-10-17 16:29:57 -04:00
7c541c704a
usdrx1: ZC706, Update project to the new GT framework
2016-10-14 18:08:08 +03:00
1d1fe26624
fmcomms7: ZC706, Update project to new GT framework
2016-10-14 17:32:23 +03:00
5bb77109ca
daq2/a10gx- make fix
2016-10-10 13:03:44 -04:00
905e29eb01
hdlmake- altera
2016-10-10 12:55:55 -04:00
e5cf417576
daq2/mb- xcvr procedures
2016-10-10 12:51:30 -04:00
273073a584
daq2/kcu105- xcvr procedure
2016-10-10 11:12:47 -04:00
b3d3876dc5
imageon: ZC706, updated system_top to remove part of the Warnings.
...
- constraints fixed so Vivado doesn't issue a Warning
2016-10-10 17:33:42 +03:00
9efc45f0b6
imageon: Zed, updated system_top to remove part of the Warnings.
...
- spi csn signals should be tied to 1 if spi is not used
- constraints fixed so Vivado doesn't issue a Warning
2016-10-10 17:31:25 +03:00
8875c5bef3
fmcomms6: ZC706, updated system_top to remove part of the Warnings
2016-10-10 16:43:23 +03:00
fcd56a2f90
daq3/a10gx: Update project to the new GT framework
...
- Update common script
- Update system_top, some port names were changed
- Update constraint files
2016-10-10 16:22:08 +03:00
94f55f20e9
adv7511: KCU105, updated system_top to remove part of the Warnings
2016-10-10 16:12:17 +03:00
f464497062
cn0363: Microzed, updated system_top to remove part of the Warnings
2016-10-10 16:08:59 +03:00
2e605fc060
cn0363: Zed, update system_top to remove part of the Warnings
2016-10-10 15:56:46 +03:00
a12d34a98b
adv7511: Zed, updated system_top to remove part of the Warnings
2016-10-10 15:54:34 +03:00
c737afebf8
adv7511: KC705, updated system_top to remove part of the Warnings
2016-10-10 13:24:40 +03:00
74faac9210
ad9467_fmc: KC705, updated system_top to remove part of the Warnings
2016-10-10 13:19:55 +03:00
ffaf78665f
daq2- xcvr procedures
2016-10-06 14:44:20 -04:00
3b55822db3
daq2- xcvr connect
2016-10-06 14:09:27 -04:00
721ee98a06
zcu102- misc fixes
2016-10-06 10:18:14 -04:00
8965bcffb7
make: Update make files for DAQ3
2016-10-06 10:27:00 +03:00
9ace02a227
daq3/a10gx: Update project to the new GT framework
2016-10-06 10:25:25 +03:00
58c4abd8af
daq3/kcu105: Update project to the new GT framework
2016-10-06 10:23:52 +03:00
ca4dca87e2
daq2- updates
2016-10-05 14:02:59 -04:00
baabe20766
common/zcu102- spi connections & clock
2016-10-05 14:01:59 -04:00
bab9b2df0b
daq3/zc706: Update project with the new transceiver modules
2016-10-05 17:41:25 +03:00
c196b5bf68
ad6676evb: VC707, fixed system top gpio_bd datawidth
2016-10-05 15:50:43 +03:00
0208335ef3
hdlmake- updates
2016-09-30 13:20:22 -04:00
27c9bdddb6
daq2/zcu102- 2016.2 updates
2016-09-30 11:55:10 -04:00
8e1034946f
fmcomms2/zcu102- 2016.2 updates
2016-09-30 11:55:10 -04:00
9afff7ae60
common/zcu102- 2016.2 updates
2016-09-30 11:55:10 -04:00
33f9ed33c7
projects- ultrascale+
2016-09-30 11:55:10 -04:00
0ded52d8f6
daq2/zcu102- kcu105 copy
2016-09-30 11:55:10 -04:00
7290bcc81a
hdlmake- updates
2016-09-29 11:50:58 -04:00
4950c6c773
adrv9371x - xcvr updates
2016-09-29 11:50:58 -04:00
4a5b7fc723
scripts- reconnect added
2016-09-29 11:50:58 -04:00
e40311eee9
adrv9371x: A10soc, connected DMAs through 128 bit SDRAM0 port at 175MHz
2016-09-29 09:14:37 +01:00
4239f64125
dacfifo- board pin warnings
2016-09-27 14:49:20 -04:00
751a66eb72
plddr3/zc706- board pin warning
2016-09-26 15:20:37 -04:00
79b9e21be8
board- xcvr procedure
2016-09-26 15:20:18 -04:00
8314efd4e9
fmcomms11- xcvr updates
2016-09-26 15:19:29 -04:00
7fd9280cbf
fmcomms11- xcvr updates
2016-09-26 15:19:05 -04:00
f5809b8817
adrv9371x: a10soc, added adcfifos; connected the new reset to all peripherals; used the new f2sdram1 port
2016-09-24 10:09:05 +03:00
2d307d5f58
a10soc: Added system reset bridge. Using F2SDRAM port used in the previous Qsys design
2016-09-24 10:06:35 +03:00
df37a23a48
pzsdr/ccfmc- rgmii critical warnings fix
2016-09-22 11:38:43 -04:00
dc6f7bbc4e
pzsdr/ccfmc - loopback updates
2016-09-22 11:18:13 -04:00
0e2572bbd8
pzsdr- ccbrk_cmos- loopback changes
2016-09-21 13:16:04 -04:00
14ad1ea741
pzsdr- swap clear-up
2016-09-21 13:15:40 -04:00
21b5e9c634
hdlmake- updates
2016-09-21 11:56:03 -04:00
143423e3b9
adrv9371x: A10SOC, fix Makefile and system scripts to be compatible with altera
2016-09-21 18:13:02 +03:00
500d8bfb90
adrv9371x: A10GX, fix makefile and system_qsys.tcl script
2016-09-21 18:11:35 +03:00
79f34c9de7
ccbrk- test updates
2016-09-21 11:04:22 -04:00
a2e60cf693
ccbrk - test
2016-09-21 11:04:22 -04:00
3ca9fe0919
sdrstk- remove critical warnings from ps7
2016-09-16 14:06:12 -04:00
f1e787f86b
fmcomms2: TDD control is enabled by default
2016-09-16 14:45:39 +03:00
2a7bc31c01
pzsdr1- disable gpreg constraints
2016-09-15 13:49:04 -04:00
67d4e71ff0
pzsdr1- disable gpreg constraints
2016-09-15 12:41:40 -04:00
16ee1336c3
Makefile: Update make files
2016-09-15 11:41:06 +03:00
631923e9f0
usb_fx3: Update to Vivado 2016.2
2016-09-14 15:41:27 +03:00
9118ca3986
version_upgrade: Update MOTCON2 to 2016.2
2016-09-14 10:58:06 +03:00
cf9ac730a8
pzsdr1- new rev. board delays
2016-09-13 10:32:13 -04:00
9a2d2e8a02
version_upgrade: Update FMCADC4 to 2016.2
2016-09-13 15:04:11 +03:00
236a938425
daq2/a10gx- qsys updates
2016-09-12 14:57:50 -04:00
5df30ac6b0
daq2/a10gx- xcvr sharing
2016-09-12 14:57:50 -04:00
521c41ce32
adrv9371x: Updated a10soc project. Common design differentiates between nios and a10soc carrier
2016-09-08 11:44:45 +03:00
40c9fc92c1
a10soc: Switched to tcl flow
2016-09-08 11:31:06 +03:00
0d095f5da9
a10gx: Added system_type variable in common design
2016-09-08 11:29:14 +03:00
bae63ae5b1
version_upgrade: Update the DAQ3 project to 2016.2
2016-09-06 11:41:37 +03:00
b8c34791d5
version_upgrade: fmcjesdadc1 updated to 2016.2
...
Xilinx IP core JESD204 is updated to version 7.0
2016-09-06 11:41:37 +03:00
b837883b98
pzsdr1/pzsdr1/pzsdr1_cmos_system_constr: Fixed voltage level selection
2016-09-01 17:16:59 +03:00
93fa5aeec3
fmcadc2/vc707: Add adf4355 access, update design to Vivado 2016.2
2016-09-01 16:11:39 +03:00
dc21384002
pzsdr: Update ccpci base design
2016-09-01 09:06:30 +03:00
2f9ac4a342
altera- qsys-script does not support most tcl commands
2016-08-30 11:50:36 -04:00
917da79da1
altera- source defaults for qsys-script
2016-08-30 11:50:36 -04:00
8192e755e1
altera- defaults
2016-08-30 11:50:36 -04:00
1eccf5af07
fmcomms7: Update common design to Vivado 2016.2
2016-08-30 16:46:15 +03:00
2015bcedaa
fmcadc2: Update common design to Vivado 2016.2
2016-08-30 16:42:58 +03:00
6f0d124861
fmcadc5: Update to Vivado 2016.2
2016-08-30 16:09:28 +03:00
4248b9373a
ad6676evb: Update to Vivado 2016.2
2016-08-30 16:08:07 +03:00
a6e6b3f96e
version_upgrade: Update fmcomms1 common design to Vivado 2016.2
2016-08-29 15:59:15 +03:00
2e59f377e1
version_upgrade: Update ac701, mitx045 and zed common design to Vivado 2016.2
2016-08-29 09:50:46 +03:00
271029768c
pzsdr/cmos - swap==1
2016-08-26 10:31:00 -04:00
d18f6aa816
adrv9371x: A10GX, added adcfifo
...
- connected dac dma to 133 MHz clock
- set explicit clock rate to xcvr reference clock bridge
2016-08-26 14:46:48 +03:00
5cc2ab37a5
version_upgrade: Common ZC702 get an upgrade to 2016.2
...
Xilinx IP Clock Wizard updated to version 5.3
2016-08-26 10:20:04 +03:00
cd0c981b50
projects/scripts: Fix to prevent a warning
...
In case of axi_interconnects, when just one slave and master interface is
active, the 'Interconnect Optimization Strategy' is disabled. So this
parameter should be set just if there is more than one slave interface.
2016-08-26 10:08:00 +03:00
6ab137a0e9
projects/scripts: Cosmetics
2016-08-26 10:07:08 +03:00
9dfcfe6146
version_upgrade: adv7511 common script to 2016.2
...
Xilinx IP Clock Wizard updated to version 5.3
2016-08-26 09:52:01 +03:00
264bde77ad
sdrstk- SWAP==1 option
2016-08-24 12:07:13 -04:00
3c6cfdc7b5
adrv9371x: A10GX, switched TX lanes
2016-08-24 18:06:14 +03:00
215edb11c6
adrv9371: A10GX, updated design
...
- disable reconfiguration for RX transceivers and enabled the reconfiguration for TX transceiver. They cannot be enabled at the same time at this point
- update FIFO SIZE to 16 for all DMAs
- updated memory connections to 256 bit and moved clock connection to 133 MHz, for all DMAs.
2016-08-23 18:25:48 +03:00
320f87d63b
sdrstk- fix spi/port connections
2016-08-22 16:52:43 -04:00
270f8a6bbe
adrv9371x: Updated project common
2016-08-22 16:58:21 +03:00
f1b834ab25
scripts: Update script so that all interconnects are optimized for performance
2016-08-22 16:56:02 +03:00
c6b065c349
zc706: Updated DDR3 dacfifo
2016-08-22 16:48:52 +03:00
f697490de6
hdlmake- updates
2016-08-19 15:59:41 -04:00
5c35012f54
sdrstk- updates
2016-08-19 15:59:13 -04:00
8582517712
sdrstk- updates
2016-08-19 15:56:48 -04:00
67bf8f8e78
scripts- fix path and device defaults and override
2016-08-19 15:56:07 -04:00
6ef9555909
sdrstk- added
2016-08-19 13:45:40 -04:00
41203d07e9
adrv9371x: A10GX, update SPI connection
2016-08-18 17:42:27 +03:00
03c83b59bf
adrv9371x/a10soc: Export axi_ad9371_s and xcvr_reconfig_avmm
2016-08-17 19:03:53 +03:00
5d0e08d92e
common/vc707- 2016.2 version
2016-08-17 10:36:19 -04:00
73413366bc
daq2/all - warnings fix
2016-08-17 10:36:00 -04:00
0b6fbf2208
daq2/vc707- 2016.2 updates
2016-08-17 10:34:06 -04:00
ce1fed1ce6
dmafifo- adc/dac split
2016-08-16 12:54:39 -04:00
0694a5015d
kc705- 2016.2 version
2016-08-16 12:54:39 -04:00
8311098384
daq2/kc705- adxcvr changes
2016-08-16 12:54:39 -04:00
8464816c82
dmafifo-split to adc/dac
2016-08-16 12:54:39 -04:00
eb55f600fb
adrv9371x: Initial commit
...
-need to fix dc filter module for AD9371 / altera
2016-08-16 15:50:46 +03:00
5c27ccd1fa
adrv9371x: Added common qsys tcl
2016-08-16 15:34:10 +03:00
4658686ae1
adrv9371x/a10soc: Misc changes for being able to run Linux
2016-08-16 11:56:25 +03:00
39c1c83d00
adrv9371x/a10soc: Fix spi_csn assignment
2016-08-12 10:07:11 +03:00
0b0aa8e6c0
Makefile: Add MMU option to altera makefiles
2016-08-11 17:46:54 +03:00
5d93e542ed
daq2-kcu105: 2016.2 updates
2016-08-11 10:00:41 -04:00
16ad0f4379
kcu105- 2016.2 update
2016-08-11 10:00:41 -04:00
285059aed0
kcu105: Don't use phy reset automation, as it's not supported for KCU105
2016-08-09 10:19:57 +03:00
452d4706d3
kcu105: Update base project to 2015.4.2
...
- change part to revision 1.1 of the board
2016-08-09 10:19:36 +03:00
c6f4def93d
altera- make mmu a make switch
2016-08-08 11:54:51 -04:00
0cd608a7e2
lib_refactoring: Update Make files
2016-08-08 16:38:38 +03:00
df36902713
lib_refactoring: Fix path of the IO macros
2016-08-08 15:07:19 +03:00
f784557895
lib_refactoring: IOBUF is a Xilinx macro, no need to use with Altera
2016-08-08 15:06:34 +03:00
8f61e11a70
pzsdr: ccpci: Add PCIe reset monitor
...
For reliable and correct operation it is vital that the FPGA is fully
configured and up and running before the PCIe host de-asserts the reset.
Add a small logic circuit that detects de-assertion of the reset signal
that can be used to verify that the reset de-assertion was seen by the
FPGA.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2016-08-05 18:31:40 +02:00
91782989ad
pzsdr: ccpci: Set IO standard to LVCMOS33 for banks 12 and 13
...
The IO voltage for bank 12 and 13 is 3.3V on the PCIe carrier. Set the
IOSTANDARD of the pins on these banks accordingly.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2016-08-05 18:31:40 +02:00
418217dd10
pzsdr: Remove LED and button signals from PCIe carrier
...
Only the FMC carrier and the breakout board do have push buttons and LEDs.
They are not present on the PCIe carrier. So move the constraints to a
separate file that can be included by the projects that need them and
remove all LED and button related signals from the PCIe project.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2016-08-05 18:31:40 +02:00
3cff0fa7dc
pzsdr: ccpci: Use PL SPI and GPIO peripherals
...
To be able to access the GPIO pins and the SPI port through the PCIe bridge
we need to use the PL SPI and GPIO controllers rather than the PS
controllers. Adjust the sytem_top.v accordingly so that the PL peripherals
are connected to the external pins.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2016-08-05 18:29:42 +02:00
d60bce654c
Makefiles: Updated Makefiles so they run correctly with gnuwin32 tools
2016-08-05 15:16:04 +03:00
e42b4ea378
hdlmake- updates
2016-08-04 13:28:25 -04:00
ed9e92621c
daq2- spi+xcvr address conflict
2016-08-04 10:50:31 -04:00
999eccc134
daq3: Update A10GX project to Quartus 16.0
2016-08-01 16:19:43 +03:00
9a563de8ff
daq2: A10GX updated project to Quartus 16.0
...
- connected directly axi_ad9680 to xcvr_core, skipping axi_jesd_xcvr
2016-08-01 15:09:53 +03:00
52ae3ddd6c
a10gx: Updated common files to 16.0
2016-08-01 15:08:12 +03:00
7ca8e10004
make: Update Make files
2016-08-01 14:24:48 +03:00
af4c43b6e1
hdl-vivado-2016.2: Update fmcomms2 and pzsdr base design
2016-08-01 13:49:12 +03:00
fbe3d75eb0
cosmetics: Delete trailing whitespace characters
2016-08-01 13:46:46 +03:00
9952a94efb
hdl-vivado-2016.2- ip version updates
2016-07-28 13:44:57 -04:00
6ffe59728b
hdl-vivado-2016.2- update
2016-07-28 13:44:57 -04:00
3b2bde2fa1
hdl-vivado-2016.2- min. addr-space requirement
2016-07-28 13:44:57 -04:00
08f4ba24d5
usb_fx3: Switch PS7 UART to UARTLITE to communicate with the FX3 board
2016-07-28 15:21:38 +03:00
39a5534e00
hdlmake- updates
2016-07-21 16:10:38 -04:00
6df5ba1a7a
daq2- adxcvr version
2016-07-21 16:09:33 -04:00
4532e5c0cb
fmcomms11- support iq mode
2016-07-21 11:58:03 -04:00
c75289be21
fmcomms11- use qpll tx-12g5, cpll rx-6g25
2016-07-19 16:21:49 -04:00
d6243f3d01
update in fmcomms11 tcl and clock constrains
2016-07-18 09:04:13 -04:00
44d9f98e12
adi_project.pl: Fix ADI_NO_BITSTREAM_COMPRESSION detection logic
...
Only enable bitstream compression only if both the
ADI_NO_BITSTREAM_COMPRESSION environment and TCL variable are not set.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2016-07-14 10:44:42 +02:00
62c7114d77
Enable bitstream compression for Xilinx projects
...
Enabling bitstream compression reduces the size of the generated bitstream.
This means on one hand it will consume less storage, which is especially
useful for the BOOT partition of the ADI images where we store BOOT.BIN
files for all supported platforms.
On the other hand a smaller bitstream is faster to load from the storage
medium and it is also faster to program to the FPGA. So it reduces the
overall boot time as well.
The only downside of bitstream compression is that the bitstream size is no
longer constant, but depends on the actual design and resource utilization.
This will not work with bootloaders that expect a fixed size.
When building a bitstream using the tcl scripts bitstream compression can
be disabled by setting the ADI_NO_BITSTREAM_COMPRESSION environment
variable.
Initial tests show a reduction of a round 50% in size for most ADI
projects.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2016-07-14 10:16:15 +02:00
12abe2b6b9
fmcomms2: Makefile update
2016-07-12 09:39:24 +03:00
283bf9ad75
fmcomms2_a10GX: Add fmcomms2 on a10gx
2016-07-11 18:37:18 +03:00
e9fe752b7a
fmcomms2_qsys.tcl: Add fmcomms2 block design script for Altera
2016-07-11 18:34:21 +03:00
92c580a84d
daq3: A10GX, updated project to the TCL flow
2016-07-08 12:00:37 +03:00
7be017baa3
daq1: Add AXI PLDDR FIFO to the receive path
...
The AD9684 has two 500 MSPS converter, the system can not handle this
throughput without a FIFO.
2016-07-07 07:15:54 +03:00
9169e20b5e
daq1: Fix the data width on the DMAC interfaces
...
+ HP ports maximum width is 64 bits
+ DMAC's default width is 64, no need for redefinition
2016-07-07 07:15:54 +03:00
48762519b5
make updates
2016-07-06 15:02:00 -04:00
427cc84bb2
axi_ad7616: Rename the physical interface signals to rx_*
...
No functional modification.
2016-07-01 14:45:23 +03:00
69a68a99e0
imageon/zed - remove onboard hdmi and update design
2016-07-01 14:11:49 +03:00
ad491ec04a
updated tcl files after inclusion of ad9162 core
2016-06-30 13:26:16 -04:00
c6c3622816
a10gx: Updated common design adding explicit clock frequency and synchronous reset deassertion
2016-06-30 10:59:29 +03:00
8d558b2538
make: Update Make files
2016-06-29 14:50:07 +03:00
e6494b9a74
axi_ad7616: Change the DMA interface type to Write FIFO
2016-06-29 14:11:02 +03:00
64633e519c
Merge remote-tracking branch 'origin/dev_ad7616' into dev
2016-06-29 12:32:39 +03:00
2e80dec513
adrv9371x/zc706: Update project with the new axi_dacfifo
2016-06-22 12:33:47 +03:00
67c948e821
fmcomms2/a10soc-- bad board design
2016-06-14 12:29:36 -04:00
8f48a5520a
makefile updates
2016-06-10 14:26:46 -04:00
eaf4d4a19d
makefile updates
2016-06-10 14:26:14 -04:00
1746701d45
fmcomms11- updates
2016-06-10 14:20:43 -04:00
509f031d58
fmcomms11- updates
2016-06-10 14:20:43 -04:00
fdc1240cc8
fmcomms11- spi
2016-06-10 14:20:43 -04:00
8f00760c13
fmcomms11- initial commit
2016-06-10 14:20:43 -04:00
f84fafaaac
adrv9371x/zc706: Fix system top
...
The dac_fifo_bypass gpio is an internal gpio only. No need for IOBUF.
2016-06-10 10:11:27 +03:00
468800bb38
daq2/a10gx- makefile update
2016-06-07 14:06:42 -04:00
625052f46e
daq2/a10gx- qsys updates
2016-06-07 12:28:04 -04:00
d53b06849e
daq2/a10gx- qsys updates
2016-06-07 12:28:04 -04:00
ae1dd1d58e
daq2/a10gx- qsys updates
2016-06-07 12:28:04 -04:00
3516ec28b7
daq2/a10gx- qsys updates
2016-06-07 12:28:04 -04:00
3351ff607e
adrv9371x- need to investigate merge with avalon
2016-06-02 16:22:53 -04:00
ebdc7832a7
hdl make updates
2016-06-01 14:00:30 -04:00
bfeebc2791
imageon/zc706- remove onboard hdmi
2016-06-01 13:59:13 -04:00
eca4d4e2a6
imageon/zc706- board updates
2016-06-01 13:59:13 -04:00
c293c04634
hdl make updates
2016-06-01 13:53:09 -04:00
46b464ed72
adrv9371/a10soc- qsys updates
2016-06-01 13:48:51 -04:00
a958ef27da
adrv9371- qsys updates
2016-06-01 13:48:51 -04:00
5b2a90ffff
adrv9371- qsys
2016-06-01 13:48:51 -04:00
af45acfcb9
ad9371- qsys updates
2016-06-01 13:48:51 -04:00
d2fc64d130
daq3/a10gx: updates
2016-05-27 08:37:47 -04:00
d10dd78094
kcu105: Update common design to 2015.4
2016-05-27 14:59:28 +03:00
1853c6921d
adrv9371x/zc706: Fix typo in system_top
2016-05-27 14:13:55 +03:00
a6fbf6c20b
adrv9371x: Update the Makefiles
2016-05-27 14:13:55 +03:00
32d46389f2
adrv9371x: Move GTs AXI interface to HP3
...
If the VDMA and the GTs AXI are connected to the same HP port, the
HDMI won't work on full resolution (1080p). Care should be taken, this can
affect the receive and observation paths (both are connected to HP2).
2016-05-27 14:13:55 +03:00
b452a8e2d4
adrv9371x: Connect bypass and data underflow
2016-05-27 14:13:55 +03:00
3859cba186
adrv9371x/zc706: Add PL_DDR FIFO to the design
2016-05-27 14:13:55 +03:00
d0b40afb45
zc706/common: Fix PL_DDR3 fifo integration script
2016-05-27 14:13:55 +03:00
aca3038919
axi_dacfifo: No overflow for DAC
2016-05-27 14:13:55 +03:00
81ade7f26c
axi_dacfifo: Fix resets
...
DMA side: axi_resetn is used to reset the address counters
DAC side: GT tx_rst is used to reset the last_address register
2016-05-27 14:13:55 +03:00
578376c8fe
axi_dacfifo: Add bypass logic
2016-05-27 14:13:55 +03:00
9c6e80fca2
daq3/a10gx- qsys modifications
2016-05-24 03:15:45 -04:00
39d23032f1
daq2- qsys updates
2016-05-23 10:55:44 -04:00
0d1c4d232e
a10soc- updates-1
2016-05-20 16:14:57 -04:00
09520709b0
make updates
2016-05-20 12:35:45 -04:00
f92e8509bb
adrv9371x- added
2016-05-20 11:46:25 -04:00
50d018fc11
arradio- rfifo/wfifo added
2016-05-18 13:24:13 -04:00
e345953bdd
arradio- updates
2016-05-16 12:19:38 -04:00
72151bb1a6
a10gx: Updated base design to include MMU
2016-05-13 18:44:41 +03:00
f3f5353944
zcu102- updates
2016-05-10 15:40:41 -04:00
16e3a0e569
zcu102- updates
2016-05-10 15:40:41 -04:00
e1350018da
zcu102- updates
2016-05-10 15:40:41 -04:00
a6411dbd63
zcu102- added
2016-05-10 15:40:41 -04:00
e8fbdd0f5d
zcu102: zynq ultrascale
2016-05-10 15:40:41 -04:00
0041bf69be
c5soc- remove unused hps ports
2016-05-09 13:54:08 -04:00
89b20f2a35
c5soc- remove unused hps ports
2016-05-09 13:54:08 -04:00
8d72b645ae
fmcomms2/common: Remove ila_tdd block
2016-05-09 10:28:10 +03:00
b0538a03a2
Make: Update
2016-05-06 16:44:24 +03:00
4863a04132
axi_adc/dacfifo: Split the intergration script file
...
Split the integration script file into two separate script files. Rename the
integration processes names to be more meaningful.
2016-05-05 09:53:55 +03:00
ddfaff2cf5
fmcomms2/a10soc: compile version
2016-05-04 13:42:12 -04:00
f4e5965936
fmcomms2/a10soc: ip updates
2016-05-04 13:42:12 -04:00
92dcce1674
a10soc: default ports
2016-05-04 13:42:12 -04:00
be74db656c
ad6674evb, fmcadc2, fmcadc4, fmcadc5, fmcjesdadc1:
...
Update system_project.tcl scripts to correctly select the necessary
constraint files
2016-05-04 19:37:33 +03:00
3ca3414522
fmcadc2: Fixed bus data width
2016-05-04 19:20:01 +03:00
9104b2cc60
ad6676evb, fmcadc2, fmcadc4, fmcadc5,...
...
ad6676evb, fmcadc2, fmcadc4, fmcadc5, fmcjesdadc1: Remove unused
set_proprieties
2016-05-04 19:13:25 +03:00
385ed31a45
make files update
2016-04-29 10:17:35 -04:00
61b531b1c1
a10soc device update
2016-04-29 10:17:35 -04:00
160d54f311
ad7616_sdz: Some comment rephrase
2016-04-29 16:41:35 +03:00
664ea16a0f
ccpci- carrier changes
2016-04-27 16:26:11 -04:00
e790e4c3ae
a10soc- complete qsys
2016-04-25 12:56:19 -04:00
bfa6fe2a40
a10soc- updates
2016-04-25 11:23:16 -04:00
28159aeec9
a10soc- updates
2016-04-25 11:11:46 -04:00
0a3967b886
a10soc- updates
2016-04-25 10:53:26 -04:00
d36d1263c5
a10soc- updates
2016-04-25 10:50:09 -04:00
1fd5c0f28b
ad7616_sdz: Fix IO definitions for the parallel interface.
2016-04-25 10:56:45 +03:00
6de356e8fc
ad7616_sdz: Fix the data width at i_iobuf_adc_cntrl
2016-04-25 10:55:37 +03:00
2a5f31d26b
fmcomms2/a10soc- copy
2016-04-22 15:15:44 -04:00
82c4f75f13
a10soc- a10gx copy
2016-04-22 10:39:21 -04:00
7a4a7edfba
daq2/a10gx: 10AX115S3F45E2SGE3 version
2016-04-20 16:07:41 -04:00
e00236e5fd
daq2/a10gx: 10AX115S3F45E2SGE3 version
2016-04-20 16:04:46 -04:00
8b2542b181
daq2/a10gx: 10AX115S3F45E2SGE3 version
2016-04-20 16:01:12 -04:00
679d471d75
Merge branch 'hdl_2016_r1' into dev
...
hdl_2016_r1 contains IP core upgrades to Vivado 2015.4.2 and hdmi_tx improvements.
2016-04-19 18:05:50 +03:00
402253d308
usb_fx3: Updated design to include the GPIF II interface
2016-04-19 15:52:30 +03:00
8a574cd8ba
zc706_system_plddr3.tcl : Add integration process for the AXI_DAC_FIFO
2016-04-19 11:30:52 +03:00
c291f8f107
daq1: Updated design to 2015.4
2016-04-14 23:36:47 +03:00
469b4ea5e8
fmcadc5: Updated design to 2015.4
2016-04-14 23:18:23 +03:00
62bd057106
fmcadc5/common: Update common design to 2015.4
2016-04-14 23:01:38 +03:00
a88ced8136
pzsdr1: lvds/cmos updates
2016-04-11 16:18:29 -04:00
3006c5a223
make updates
2016-04-11 16:14:59 -04:00
736bbdd95a
pzsdr1- io updates
2016-04-11 16:12:21 -04:00
8a5a5082f3
pzsdr1- io updates
2016-04-11 16:12:09 -04:00
8e689f4594
pzsdr1- lvds/cmos constraints
2016-04-11 16:00:18 -04:00
7e807d83b1
pzsdr1- cmos mode
2016-04-11 15:58:29 -04:00
bf6ef4e5f3
board- add disconnect
2016-04-11 15:33:00 -04:00
68bc647472
pzsdr1- ddr board delays update
2016-04-06 15:30:27 -04:00
21208ca208
Makefiles: Update Makefiles
2016-03-31 12:37:47 +03:00
1fab6ce477
daq2/common: Add util_dacfifo/dac_xfer_out control
2016-03-29 16:55:33 +03:00
255b0ebd40
util_dacfifo: Add dac_xfer_out control
...
The dac_xfer_out control signal is asserted while the DAC reads back data. Should be connected to upack/dma_xfer_in.
2016-03-29 16:50:00 +03:00
657144d9a7
a10gx: Updated base design and DAQ2 to the new revision of the a10gx board
...
- tried using ATX PLL and fPLL for TX transceiver clocks, but could not get them to lock
- CMU PLL works correctly as temporary solution
2016-03-28 13:21:36 +03:00
7ce3f6e274
ad7616_sdz: Fix system top for parallel interface mode.
2016-03-24 13:49:30 +02:00
a1c2c61884
ad7616_sdz: Update the IOBUF instance names
2016-03-24 11:46:33 +02:00
7c2f34549b
motcon2_fmc: Update common design to 2015.4
2016-03-23 10:27:07 +02:00
373481360b
util_dacfifo: Add a bypass option to the FIFO
2016-03-21 14:14:43 +02:00
714caa964c
usdrx1: Update common design to 2015.4
2016-03-18 16:29:43 +02:00
05f4f3ac09
usb_fx3: Update common design to 2015.4
2016-03-18 16:16:38 +02:00
24fdd2b9b7
pzsdr/ccpci: Update common design to 2015.4
2016-03-18 15:30:10 +02:00
f8b155faab
pzsdr/ccfmc: Update common design to 2015.4
2016-03-18 15:28:56 +02:00
d567af54ef
imageon: Update common design to 2015.4
2016-03-18 15:27:31 +02:00
995debedce
fmcomms2: Update common design to 2015.4
2016-03-18 15:26:52 +02:00
b555be25d5
kcu105: Update common design to 2015.4
2016-03-18 15:22:42 +02:00
412013d939
adv7511: Update common design to 2015.4
2016-03-18 15:01:25 +02:00
d355aa0ea6
daq3/zc706: Updated design to 2015.4
2016-03-17 11:46:48 +02:00
012b095006
daq3: Updated common design to 2015.4
2016-03-17 11:44:27 +02:00
38c3f7474a
ad6676: Updated common design to 2015.4
2016-03-17 11:40:46 +02:00
abc03fff2c
fmcomms7: Updated design to 2015.4
2016-03-17 09:11:41 +02:00
59c726ecbe
fmcjesdadc1: Updated common design to 2015.4
2016-03-16 10:14:06 +02:00
1a3aab0c13
fmcomms1: Updated common design to 2015.4
2016-03-16 10:09:54 +02:00
b7be089b82
daq2: Updated common design to 2015.4
2016-03-16 10:02:42 +02:00
697469ee28
daq1- updates
2016-03-15 12:39:38 -04:00
334fce03a3
fmcadc4/zc706: Updated design to 2015.4
2016-03-15 15:28:11 +02:00
e8dd5f9788
fmcadc4: Updated common design to 2015.4
2016-03-15 15:27:25 +02:00
98cc7dad7d
fmcadc2: Updated common design to 2015.4
2016-03-15 15:26:05 +02:00
ceea7f25b2
fmcomms2: Updated common design to 2015.4
2016-03-15 15:23:20 +02:00
6f03998b95
zc702: Updated common design to 2015.4
2016-03-15 15:21:22 +02:00
a0c5f46940
zed: Updated common design to 2015.4
2016-03-15 15:20:46 +02:00
9a258d5e4c
vc707: Updated common design to 2015.4
2016-03-15 15:20:02 +02:00
bcf5bd8137
mitx045: Updated common design to 2015.4
2016-03-15 15:18:31 +02:00
27f5f1dcbe
kc705: Updated common design to 2015.4
2016-03-15 15:17:53 +02:00
eb743e0e03
ac701: Updated common design to 2015.4
2016-03-15 15:17:02 +02:00
d282064103
zc706: Updated common design to 2015.4
2016-03-15 15:16:36 +02:00
71be9519ec
adi_project.tcl: Updated to 2015.4
2016-03-15 15:03:50 +02:00
33b265a742
Makefile: Update Makefiles
2016-03-14 09:31:17 +02:00
561412e322
pzsdr-cmos swap
2016-03-11 11:25:58 -05:00
c7ee15d4f4
ccbrk_cmos: cmos mode
2016-03-11 11:25:58 -05:00
c566784ba9
ccbrk_cmos: ccbrk copy
2016-03-11 11:25:58 -05:00
573146aa96
axi_ad7616: Fix the data width of the AXI stream interface
2016-03-10 16:38:53 +02:00
b0f90bd0e8
daq1/cpld: Read interface fix
2016-03-04 20:28:24 +02:00
7e607957ee
daq1.cpld: Prevent the spi_counter to roll over.
2016-03-04 20:28:22 +02:00
262a42c676
daq1/cpld: Update CPLD_VERSION value
2016-03-04 20:28:20 +02:00
9439862301
daq1/cpld: Update CPLD
...
Change to control line fpga_to_cpld to cpld_to_fpga, this is not a functional change.
2016-03-04 20:28:18 +02:00
3466f21f8e
pzsdr add cmos/lvds support
2016-03-04 10:39:48 -05:00
18f30c8dc8
pzsdr- cmos/lvds split
2016-03-04 10:39:48 -05:00
a2374f64bf
pzsdr- cmos/lvds split
2016-03-04 10:39:48 -05:00
977d9d0624
Merge branch 'hdl_2015_r2' into dev
...
Conflicts:
projects/daq1/common/daq1_spi.v
2016-03-02 13:52:15 +02:00
40fb68dfd5
ad9265, ad9434, ad9467, daq1, daq2, daq3, fmcadc2, fmcadc4, fmcadc5, fmcjesdadc1, fmcomms6, fmcomms7, usdrx1: updated common spi module so that spi streaming is possible
2016-03-02 13:39:37 +02:00
becc23a69b
daq2: Modified common spi module so that spi streaming is possible
...
- stop incrementing spi_count after the instruction cycle
2016-03-01 17:25:58 +02:00
f7e490c2b3
hdlmake.pl updates
2016-02-26 13:46:11 -05:00
e012d0519b
Merge remote-tracking branch 'origin/hdl_2015_r2' into dev
2016-02-26 13:39:39 -05:00
f6e64e42b0
kcu105: add ethernet idelaycntrl
2016-02-26 13:19:49 -05:00
59313f3c90
daq1: ADC DMA must be in none-cyclic mode
2016-02-24 14:37:19 +02:00
c0a559a9b1
daq1: Fix some typos in the SPI wrapper
2016-02-24 14:31:56 +02:00
8ccd8d87bb
daq2: A10GX, increase analog/digital reset durations
...
- reset the xcvr_rst_cntrl only from the axi_jesd_xcvr
- checked separate RX/TX reset per channel
2016-02-23 11:41:38 +02:00
89f7aadfb1
fmcjesdadc1: A5GT, connected xcvr_rxt_cntrl reset input to the axi_jesd_xcvr reset output
...
This will allow for the transceivers to be reset by the axi_jesd_xcvr core
2016-02-23 11:31:07 +02:00
4fb6589b2d
pzsdr/ccfmc: add fan controls
2016-02-19 16:40:54 -05:00
377461e0d4
Merge branch 'hdl_2015_r2' into dev
2016-02-19 14:15:27 +02:00
0f37dd6424
fmcjesdadc1: Fixed project
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- changed system_project.tcl so that all base designs to be included
- changed DMA properties to take into consideration the new parameter names
- changed reset bridges to asynchronous
- increased maximum burst size of the DMA bridge
- changed the data_width of the memory bus to 256, as with 512 timing violations may occur
- changed base addresses for the base system to be the same as in the previous release
2016-02-19 14:09:57 +02:00
ce760eb691
fmcadc2- add adf4355 access
2016-02-18 16:17:33 -05:00
d94f157454
arradio: Changed ADC/DAC DMA address length to 24 bit
2016-02-16 15:27:51 +02:00
43e03ca6f7
arradio: Updated project
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- made the reset bridges asynchronous
- connected the arradio gpio to the CPU interconnect
2016-02-16 14:50:23 +02:00
5518c47ca4
daq1_cpld: Set Input and tristate I/O termination mode to FLOAT
2016-02-15 19:27:59 +02:00
051ac307e6
daq1_cpld: Do not forward the first eight clock cycles of fmc_spi_sclk to sclk
2016-02-15 19:26:58 +02:00
9370246cfa
daq1: Fix bugs on CPLD design
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Fix the CSN forwarding.
2016-02-12 16:59:09 +02:00
5ed2c0b599
daq1: Update CPLD constraints file
2016-02-12 16:54:36 +02:00
aa2ff0223a
daq1: Update CPLD design
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+ SPI counter counts on negative edge of the SPI_CLK
+ Shift register for read, shifting MSB first
+ Fix write access logic
+ Update the internal register addresses
2016-02-12 14:45:18 +02:00
c32d7147d5
daq1 : There is a single CSN from master
2016-02-12 14:38:32 +02:00
9675df15c6
daq1_zc706: Update constraints file
2016-02-12 14:37:02 +02:00
e381d5170c
util_tdd_sync: Update the synchronization interface
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Simplify the synchronization interface, there is one signal line between the synchronization module and transceiver core.
2016-02-12 14:27:37 +02:00
61f9f72a75
fmcjesdadc1: Updated VC707 project for maximum throughput from DMA to DDR
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- Increased the DMAs internal FIFO
2016-02-09 12:30:56 +02:00
c431adb793
fmcjesdadc1: Updated KC705 project for maximum throughput from DMA to DDR
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- Increased the DMA internal FIFO
2016-02-09 12:00:27 +02:00
ad9ecbbbb6
daq2: Updated a10gx project to quartus 15.1.1
2016-02-05 17:43:05 +02:00
a74e2061e9
ad7616_sdz: BUSY is input for the FPGA
2016-02-03 14:12:00 +02:00
bb62f6d225
pzsdr1- updates
2016-02-02 12:34:09 -05:00
41b6ebeeaf
pzsdr1- updates
2016-02-02 12:33:55 -05:00
b147e9c94a
pzsdr1- updates
2016-02-02 12:33:01 -05:00
59783f6cff
ad7616_sdz: Add support for Zedboard
2016-01-29 15:28:06 +02:00
122667259f
ad7616_sdz: Update Make file
2016-01-28 14:48:44 +02:00
118577f64f
ad7616_sdz: Add support for parallel interface
2016-01-28 12:38:22 +02:00
170295161f
pzsdr1- xdc
2016-01-26 11:19:00 -05:00
cd43ebd8bc
axi_ad7616: The OP_MODE parameter is no longer required
2016-01-26 11:05:33 +02:00
bcac3eef4d
pzsdr1- initial commit
2016-01-25 16:07:33 -05:00
44a382fc69
pzsdr1-added
2016-01-25 15:33:34 -05:00
2a17ce275c
axi_ad7616: Control inputs are controlled through GPIO
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The following control inputs are controlled through GPIO: reset_n, seq_en, hw_rngsel, chsel, crcen, burst and os.
2016-01-25 17:50:50 +02:00
e22d5d5c18
daq2: Fix clock constraints for KC705 and VC707
2016-01-22 19:09:57 +02:00
59fbd99fdb
fmcjesdadc1: Added clock constraint for the ADC path
2016-01-22 15:46:20 +02:00
dca39c26f9
ad6676evb: Added clock constraint for the ADC path
2016-01-22 15:45:16 +02:00
9cd0378003
fmcadc2: Added clock constraint for the ADC path
2016-01-22 15:44:04 +02:00
aa77af6bdf
daq1_cpld: Add ISE project file
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This file, along with the project source files, is sufficient to open and implement in ISE Project Navigator.
2016-01-21 18:05:59 +02:00
14f7027793
ad7616_sdz: Move the context switching to system_project.tcl
2016-01-19 11:34:28 +02:00
8c69c9d2ce
daq1_zc706 : Update the project
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+ Add AD9684 to the block design
+ Update the IO definitions
+ Update the CPLD design
+ Add 3wire SPI logic
2016-01-19 11:20:35 +02:00
ab99c4456a
ad9434_fmc: Delete unnecessary set_property call
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HPx interface is activated by the ad_mem_hpx_interconnect process
2016-01-14 15:41:23 +02:00
c094ab8b52
cn0363: Add support for the MicroZed
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Add support for connecting the CN0363 to the MicroZed. This works in
combination with the MicroZed Arduino carrier board. The CN0363 needs to be
connected to the PLPMOD header.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2016-01-13 20:32:26 +01:00
Adrian Costina
Rejeesh Kutty
AndreiGrozav
Istvan Csomortani
Nick Pillitteri
Lars-Peter Clausen
István Csomortáni
dbogdan
Shrutika Redkar