Commit Graph

30 Commits (af3a4f5fc9aff7b17ed090ce843b3bf5f5394578)

Author SHA1 Message Date
Istvan Csomortani 16ee1336c3 Makefile: Update make files 2016-09-15 11:41:06 +03:00
Istvan Csomortani 0cd608a7e2 lib_refactoring: Update Make files 2016-08-08 16:38:38 +03:00
Istvan Csomortani df36902713 lib_refactoring: Fix path of the IO macros 2016-08-08 15:07:19 +03:00
Adrian Costina d60bce654c Makefiles: Updated Makefiles so they run correctly with gnuwin32 tools 2016-08-05 15:16:04 +03:00
Rejeesh Kutty e42b4ea378 hdlmake- updates 2016-08-04 13:28:25 -04:00
Istvan Csomortani 7ca8e10004 make: Update Make files 2016-08-01 14:24:48 +03:00
Istvan Csomortani 7be017baa3 daq1: Add AXI PLDDR FIFO to the receive path
The AD9684 has two 500 MSPS converter, the system can not handle this
throughput without a FIFO.
2016-07-07 07:15:54 +03:00
Rejeesh Kutty 3006c5a223 make updates 2016-04-11 16:14:59 -04:00
Rejeesh Kutty 697469ee28 daq1- updates 2016-03-15 12:39:38 -04:00
Rejeesh Kutty f7e490c2b3 hdlmake.pl updates 2016-02-26 13:46:11 -05:00
Istvan Csomortani 9675df15c6 daq1_zc706: Update constraints file 2016-02-12 14:37:02 +02:00
Istvan Csomortani 8c69c9d2ce daq1_zc706 : Update the project
+ Add AD9684 to the block design
+ Update the IO definitions
+ Update the CPLD design
+ Add 3wire SPI logic
2016-01-19 11:20:35 +02:00
Adrian Costina 9d2b8809df Makefiles: Updated Makefiles 2015-10-23 10:44:27 +03:00
Adrian Costina a7da779b94 Makefile: Updated Makefiles 2015-07-16 18:19:42 +03:00
Rejeesh Kutty a6cae6b477 iobuf: do is a system verilog keyword 2015-05-21 14:06:17 -04:00
Lars-Peter Clausen 6b9906b22b Refresh Makefiles
Re-generate the Makefiles after a small update to the generation script:
- Entries are sorted alphabetically
- Empty dependency lines are skipped

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-05-21 14:21:54 +02:00
Adrian Costina c19749361d Makefiles: Updated makefiles to have as a result the programming file instead of the project file.
Also fixed altera projects dependencies
2015-05-18 17:22:46 +03:00
Adrian Costina 949abcdc8f Makefile: Updated makefiles so that the project recipe does not depend on lib 2015-05-06 14:58:29 +03:00
Adrian Costina 3b58785368 daq1: Updated jesd reset connection. Fixed dmac async configuration. Updated zc706 constraints 2015-04-30 12:14:03 +03:00
Adrian Costina dc2b37bd0c Makefile: Added top level Makefile. Modified behavior of clean and clean-all
Clean ran for a project will clean only the project files.
Clean-all ran for a project will clean also the library files on which the project depends.
The clean commands will only remove specific files and directories.

The top Makefile allows several options(per suggestion from jameyhicks):
make fmcomms1.zed will run "make all" in projects/fmcomms1/zed/
make clean will run "make clean" for all the projects
make clean-all will run "make clean" for all the projects and libraries
make lib will run "make all" for the library files
2015-04-17 17:22:38 +03:00
Adrian Costina 780455d68c Makefile: Updated makefiles. Added makefiles for altera 2015-04-09 17:57:06 +03:00
Rejeesh Kutty 5f8e9a74ea makefile: updated 2015-04-07 16:32:01 -04:00
Adrian Costina f79a152958 Makefiles: updated all makefiles adding clean functionality 2015-04-03 11:57:54 +03:00
Rejeesh Kutty 79a07e737d makefile: added 2015-04-01 16:28:56 -04:00
Istvan Csomortani 75d2c7e93e daq1_zc706: Update project to the new framework 2015-03-24 12:45:24 +02:00
Istvan Csomortani 0ecfc14e95 daq1_fmc: Update interrupts. 2014-11-24 18:23:32 +02:00
Istvan Csomortani 9b104f1657 daq1_fmc: Get rid of the concat module inside the block design.
xl_concat just causing troubles, no need to use it, if not justified.
2014-11-24 18:23:30 +02:00
Rejeesh Kutty 577441bd0c daq1: clean up dma interfaces 2014-09-23 14:23:41 -04:00
Istvan Csomortani 751bdd6cfc daq1: Update the constraint file
- tx_ref_clk and rx_sysref need to be differential
  - cosmetic changes
2014-09-19 18:22:57 +03:00
Istvan Csomortani ee752ec08a daq1: Initial commit 2014-09-01 18:34:31 +03:00