Currently the BRAM and data registers in the util_axis_data are ungated
when the FIFO is ready to receive data. This good for high-performance
since it reduces the number of control signals. But it is bad from a power
point of view since it causes additional reads and writes.
Change the core gate the BRAM and data register if either the consumer is
not ready to accept data or the producer has no data to offer.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Add a room output on the input side that reports how many free entries the
FIFO has and a level output on the output side that reports how many valid
entries are in the FIFO.
Note that the level output is only accurate if the output of the FIFO is not
registered, otherwise it might be off by one.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Add a option to specify whether the FIFO should have a registered output
stage or not. This is useful if the user wants to implement that stage
itself.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Bring back the AXIS FIFO as a separate module instead of embedding it into
the DMAC module. This makes it possible to use it in other modules outside
of the DMAC.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Lars-Peter Clausen
Istvan Csomortani