d0adbb718a
util_dacfifo: Update constraint file
...
Delete deprecated, old constraints; update the constraint flag from
'hier' to 'hierarchical'.
2018-10-16 10:29:37 +03:00
fa32ea8f1f
util_dacfifo: Fix the reset logic of the module
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Both the DMA and DAC side should be in reset at the positive edge of the
dma_xfer_req, so we can re-initialize the buffer.
2018-10-11 16:57:30 +03:00
6044aa3956
util_dacfifo: Update the bypass logic
2018-10-11 16:57:30 +03:00
660dddf1e8
util_dacfifo: Define constraints for bypass
2017-03-07 16:14:46 +02:00
760228d676
util_dacfifo: Update the util_dacfifo
...
Fix bypass and undate the general functionality. If bypass enabled
the FIFO will function as a normal CDC FIFO.
2017-03-03 18:43:36 +02:00
ac2e5a9dac
constraints: Update constraints
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Xilinx recommends that all synchronizer flip-flops have
their ASYNC_REG property set to true in order to preserve the
synchronizer cells through any logic optimization during synthesis
and implementation.
2017-02-24 13:43:32 +02:00
bb9cb86f34
adc/dac- fifo constraints
2016-08-11 10:00:41 -04:00
69d721526a
util_dacfifo: Add constraints file
2016-04-12 13:21:50 +03:00
Istvan Csomortani
Rejeesh Kutty