4c7be950d1
ad_ip_jesd204_tpl_adc: Fix latency of valid signal
2022-02-16 10:27:50 +02:00
f245448976
ad_ip_jesd204_tpl_ : Add missing dependency
2022-02-07 19:14:01 +02:00
b5092662d5
ad_ip_jesd204_tpl_adc: Refactor external sync
...
- Add EXT_SYNC option
- Gate valid while in reset
2022-02-07 19:14:01 +02:00
8c7cca4277
common/up_adc_common: Add ext sync regs
2022-02-07 19:14:01 +02:00
1b06c74919
common/up_dac_common: Add manual sync request
2022-02-07 19:14:01 +02:00
db49aa652f
common/up_dac_common: Add support for explicit disarm control
2022-02-07 19:14:01 +02:00
4e644e4e74
jesd204/ad_ip_jesd204_tpl_dac: External sync refactor
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- Expose EXT_SYNC parameter to sw
- Add external manual sync request
- Add rst to interface
2022-02-07 19:14:01 +02:00
1ca5abc91e
common/up_xfer_cntrl: Fix transfer done timing
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up_xfer_done should signalize when a previous control set is
transferred to the other clock domain and the current control set is latched.
If a bit from the up_data_cntrl changes, it should stay in that state until
the up_xfer_done asserts.
2022-02-07 19:14:01 +02:00
170ce42e3e
util_mii_to_rmii: Initial commit
2022-02-03 10:23:12 +02:00
38f3627695
ad_dds: Fix DDS start samples
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When using a CLK_RATIO > 1 the first n samples(n=CLK_RATIO) after sync, are
noisy. This is because the phase accumulator data is passed to the phase to
amplitude converter, during the phase synchronization step.
2022-01-31 14:07:11 +02:00
b26b4c00f0
ad9783: Clean-up parameters and module instances
2022-01-25 18:24:43 +02:00
889447e900
axi_ad9361: make IODELAYCTRL insertion optional
2022-01-25 09:50:31 +02:00
bc8e7881f2
axi_dmac: Hook up ID
...
Signed-off-by: Laszlo Nagy <laszlo.nagy@analog.com>
2022-01-25 09:50:22 +02:00
f3cf7508c8
ad9783: Update Makefile
2022-01-20 12:31:57 +02:00
9d94f21d89
scripts/adi_xilinx_device_info_enc.tcl: Change regex for vcu128
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The regex does not match vcu128 as Ultrascale+. It matches for Ultrascale.
2022-01-12 17:32:47 +02:00
9d8097389c
library/jesd204/jesd204_common/pipeline_stage.v: Initialize pipeline stage register
2022-01-12 13:43:20 +02:00
080925e8fe
library/jesd204: tpl timing bug fix
2022-01-12 10:14:55 +02:00
08f029c757
axi_ad9783: Initial commit
2022-01-07 14:04:08 +02:00
fcd3bfd349
util_pulse_gen: Reload registers when counter is at one
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This patch fixes an issue where the pulse width is only updated two
periods after the current one.
Signed-off-by: David Winter <david.winter@analog.com>
2022-01-04 15:02:05 +02:00
c2d960e029
axi_adrv9001: Add external sync support
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The external sync must be synchronous to the reference clock, in order
to obtain a deterministic synchronization of the interface.
2021-12-16 15:16:30 +02:00
41525f348b
axi_adrv9001/axi_adrv9001_core.v: Disable TDD and IOCTRL if second SSI interface is disabled
2021-12-08 17:31:53 +02:00
dfe153dc68
axi_adrv9001/axi_adrv9001_tdd.v: Add disable option for TDD
2021-12-08 17:31:53 +02:00
8cc0367e8f
axi_adrv9001: Hide disabled interfaces
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Signed-off-by: Laszlo Nagy <laszlo.nagy@analog.com>
2021-12-08 17:31:53 +02:00
6a4b46ebb4
axi_adrv9001: Make Rx2 and Tx2 source synchronous interfaces optional
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If the Rx2 and Tx2 SSI are disabled the rx1,tx2 data paths are forced to
R1 mode.
Signed-off-by: Laszlo Nagy <laszlo.nagy@analog.com>
2021-12-08 17:31:53 +02:00
c1ca578343
axi_ad7616: Fix sync port
2021-11-22 15:22:16 +02:00
8e0a45dea9
jesd204_rx/jesd204_lane_latency_monitor.v: Fix for datapath width of 4
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Current implementation is correct only for datapath width of 8.
The buswidth of latency measurement inside a beat has a fixed width (3 bits)
for each lane that must be taken in account when computing the total latency.
Signed-off-by: Laszlo Nagy <laszlo.nagy@analog.com>
2021-11-19 18:14:43 +02:00
7e5a638386
jesd204_versal_gt_adapter_rx/tx: Infer Versal GT interface
2021-11-19 14:01:48 +02:00
b25c37a8cc
axi_adrv9001/intel: Add dummy parameters to match Xilinx interface
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Signed-off-by: Laszlo Nagy <laszlo.nagy@analog.com>
2021-11-12 14:09:14 +02:00
36d0a8b3e8
library:util_pad: Initial version
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Data to DMA/system memory must be presented in widths of multiple of 8 bits,
however this padding is not optimal if is done in the transport layer
since this will affect the DAC/ADC FIFO or offload storage.
This utility block adds or removes padding from sample stream in case the
sample with is not multiple of 8 bits, and can be placed between the DMA
and FIFO/Offload blocks.
2021-11-10 14:03:34 +02:00
cb8cf4b3d2
jesd204/scripts: Helper procedure for TPL width calculation
2021-11-10 14:03:34 +02:00
5dd9fd4832
axi_dmac: Allow wider FIFO/AXI Stream interface
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On large projects with multiple channels the databus on the FIFO/AXI
stream interface can get wider that 1024 bits.
This commit allows a wider range for all the interfaces,
in case for the memory mapped interfaces where the range is 32-1024 the
user selects a bus width out of range that will be handled by the IPI.
2021-11-10 14:03:34 +02:00
fcb16daf5b
axi_adrv9001: Add the option of global clock buffers on 7 series
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Using global clock can help placement issues where the logic does not fits in one
clock region.
2021-11-08 13:53:51 +02:00
7112fbce7e
library/scripts/adi_xilinx_device_info_enc.tcl: Add K26 support
2021-11-08 09:23:02 +02:00
5d7f4672f5
axi_i2s_adi: initialize cdc_sync_stage0_tick bits to '0'
2021-11-08 08:52:01 +02:00
18ab43b5a1
axi_hdmi_tx: Add UltraScale+ architecture to Verilog
2021-11-08 08:52:01 +02:00
a381fe3e92
ad_ip_jesd204_tpl_adc: Add value of 14 to CONVERTER_RESOLUTION parameter
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Added new allowed value of 14 for the CONVERTER_RESOLUTION parameter.
Signed-off-by: Dan Hotoleanu <dan.hotoleanu@analog.com>
2021-11-04 12:18:06 +02:00
3c07861ee8
generate_xml.sh: Replace < and > in error message
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Replace < with < and > with > in ERRS to not broke created xml.
Signed-off-by: stefan.raus <stefan.raus@analog.com>
2021-11-03 15:22:45 +02:00
70cc53bbc8
ad_ip_jesd204_tpl_dac: Move external dac sync bit
2021-10-27 18:36:47 +03:00
7b0922e4dc
library/common/up_adc_common.v: Remove tabs
2021-10-27 18:36:47 +03:00
a9c9636780
library/common/up_dac_common.v: Cleanup spaces
2021-10-27 18:36:47 +03:00
9b7c2852b6
adxcvr: Increase version to 17.5.a
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Add suport for XCVR phase adjust buffer status:
- Expose TXBUFSTATUS and RXBUFSTATUS
- Create RXBUFSTATUS_RST flag for clearing RXBUFSTATUS
2021-10-27 14:40:50 +03:00
d493b724f2
axi_adrv9001/adrv9001_rx.v: Simplify clocking
2021-10-27 14:40:08 +03:00
6a5d2f76d5
data_offload: Fix oversized TX input transactions
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Signed-off-by: David Winter <david.winter@analog.com>
2021-10-27 14:26:22 +03:00
cd6024b341
Revert "data_offload: Fix oversized inputs in TX mode"
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This reverts commit 0e8f55b2d7
2021-10-27 14:26:22 +03:00
52df3c4937
ad463x_data_capture: Remove tb
2021-10-26 15:58:54 +03:00
076e81a17c
library: Add link to wiki for IPs
2021-10-25 10:44:53 +03:00
6a526f4bb6
ad463x_data_capture: Initial commit
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IP required to support echo and master clock mode
2021-10-18 16:13:31 +03:00
5ac64b021f
spi_engine_execution: Delete control loop-back in sdi_data_valid generation
2021-10-18 16:13:31 +03:00
6570c23a76
axi_spi_engine: Add generic config params
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The 4 parameters are added to facilitate transmiting project
related information to the software. They act as read-only
memory which is written in Vivado when the project builds.
Set 31 to SDI FIFO's almost full threshold
2021-10-18 16:13:31 +03:00
f86ae28e50
spi_engine/data_reorder: Initial commit
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In case of multiple SDI (MISO) lanes, the samples arrives in a parallel
fashion. For example in case of 4 MISO line, at the first latching clock
edge 4 bits of a sample will be saved, one bit into each shift register.
The data reorder module reconstruct the incoming samples from the AXI
stream of the offload module.
2021-10-18 16:13:31 +03:00
6565c5d018
library/tb: Improve run_tb.sh
2021-10-18 16:13:31 +03:00
e34346360d
scripts: Add logic for vivado version check
2021-10-12 14:34:11 +03:00
812baf9022
Revert "data_offload: Fix timing violation"
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This reverts commit 1fe0d5f8e0
2021-10-08 11:42:05 +03:00
dbd5ffe4ed
jesd204_rx: fixed makefile
2021-10-07 12:48:08 +03:00
0c6c28ed84
jesd204/ad_ip_jesd204_tpl : Add support for 12 lanes
2021-10-06 15:49:56 +03:00
51b643b978
Makefile: Fix misc makefiles from projects and library
2021-10-05 14:24:48 +03:00
22e1366bfc
jesd204/jesd204_rx: Define tie off values for unused ports
2021-10-05 14:09:51 +03:00
aa93c17cdc
jesd204/jesd204_tx/jesd204_tx.v: Have FFs initial value, useful for simulation
2021-10-05 14:09:51 +03:00
1a9e7dbeb4
jesd204:jesd204_versal_gt_adapter_rx/tx: Add adapter for Versal transceiver IP
2021-10-05 14:09:51 +03:00
4d12c4d99a
scripts/adi_xilinx_device_info_enc.tcl: Add Versal support
2021-10-05 14:09:51 +03:00
2b242bf06f
scripts/adi_ip_xilinx.tcl: Enable auto family support
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Some IPs like JESD link layer were marked as not supported on Versal devices by
the current flow while other not (e.g. TPL).
The auto family support seems to workaround this issue.
2021-10-05 14:09:51 +03:00
d94ec80e08
Update README.md
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Correct the ZCU102 PL DDR memory controller interface width and speed based on available options of the MIG
2021-10-05 11:59:51 +03:00
0e8f55b2d7
data_offload: Fix oversized inputs in TX mode
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This commit fixes an issue in situations where we provide an oversized
transaction to the data offload in TX mode. Previously, the data offload
would stop accepting new data (wr_ready <= 0) after filling up the
internal storage, and get stuck waiting for the input transaction to
end, thus locking up the device.
This commit addresses that issue by allowing the data offload to consume
the full input transaction, even if the tail of the buffer will be
truncated in the output.
Signed-off-by: David Winter <david.winter@analog.com>
2021-09-29 18:33:11 +03:00
7ed4955661
axi_adxcvr_ip.tcl util_adxcvr_ip.tcl: Fixed asynchronous resets critical warnings in XCVR
2021-09-28 04:53:02 +03:00
cfe0c0ced5
adi_project_xilinx.tcl, adi_ip_xilinx.tcl: update version to 2021.1
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Update vivado version from 2020.2 to 2021.1 in projects and library scripts.
2021-09-24 12:11:11 +03:00
1fe0d5f8e0
data_offload: Fix timing violation
2021-09-22 12:18:33 +03:00
cdb9a0af2b
data_offload: Add sync to cyclic mode
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Signed-off-by: David Winter <david.winter@analog.com>
2021-09-21 09:06:03 +03:00
76cd5581bc
axi_pwm_gen: Add config in soft reset option
2021-09-17 11:50:46 +03:00
591a23156b
Makefiles: Update header with the appropriate license
2021-09-16 16:50:53 +03:00
b38747cefc
Make system: Be explicit in license that cover the make/build system
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The build system is covered under a 1 Clause BSD license. Make sure
users are aware.
Signed-off-by: Robin Getz <robin.getz@analog.com>
2021-09-16 16:50:53 +03:00
12a3f8799e
JESD204 Interface Framework : add logo
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Add a small logo for branding purposes.
Signed-off-by: Robin Getz <robin.getz@analog.com>
2021-09-16 16:49:52 +03:00
1766b42a93
ad_mem_asym: Add option to control cascade layout
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Signed-off-by: David Winter <david.winter@analog.com>
2021-09-15 12:27:49 +03:00
6763ddcda9
spi_engine_execution: Fix cs signal generation
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The cs signal can now accept the IOB TRUE attribute.
2021-09-13 11:39:02 +03:00
0392013bd2
util_tdd_sync: Narrow scope of false path to D pin
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Signed-off-by: David Winter <david.winter@analog.com>
2021-09-08 11:58:24 +03:00
7423ecae14
data_offload: Improve external synchronization
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This commit adds a new synthesis option to the design, that controls
whether an internal clock domain crossing will be generated. Disabling
this option allows you to use a synchronization signal that is
synchronized to the write clock domain externally, and possibly shared
between multiple devices.
The default value retains the old behavior.
Signed-off-by: David Winter <david.winter@analog.com>
2021-09-08 11:58:01 +03:00
0372ce1821
axi_adxcvr:util_adxcvr: Correctly defined resets.
2021-09-08 11:51:59 +03:00
16a93a804b
adrv9001[intel]: Add second pair of DMAs
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fix observations for PR
2021-09-01 15:04:14 +03:00
f8c82c611d
axi_adrv9001: Add support for symbol operation mode on Xilinx devices
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Add CMOS support for the interface for the following symbol modes on Xilinx devices:
A B C D E F G H
CSSI__1-lane 1 16/8 80(SDR)/160(DDR) 80 - SDR/DDR SDR/DDR->4/2(C=16), 2/1(C=8)
Columns description:
A - SSI Modes
B - Data Lanes Per Channel
C - Serialization factor Per data lane
D - Max data lane rate(MHz)
E - Max Clock rate (MHz)
F - Max Sample Rate for I/Q (MHz)
G - Data Type
H - DDS Rate
CSSI - CMOS Source Synchronous Interface
2021-08-17 15:33:06 +03:00
8afc03abab
jesd204/ad_ip_jesd204_tpl_dac: Intel: Add support for AD916x preset files
2021-08-16 07:22:50 +03:00
1f24344620
Update Quartus version to 20.4
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Update quartus compilation tools from 20.1 to 20.4.
Remove hardcoded version from axi_adrv9001 ip.
2021-08-12 11:15:01 +03:00
235542cac9
data_offload: Fix support for > 4 GiB of storage
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This commit changes the transfer length register to work in increments of
64 bytes and without offset. The true transfer length can now be
determined by multiplying the value of the transfer_length register with
64.
A value of zero is interpreted as a request for all available storage.
Additionally, this commit fixes an off by one issue that was discovered
during testing of the RX path.
Signed-off-by: David Winter <david.winter@analog.com>
2021-08-06 11:55:24 +03:00
25038ccb4d
data_offload: Fix MEM_SIZE parameter width
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Signed-off-by: David Winter <david.winter@analog.com>
2021-08-06 11:55:24 +03:00
58953ff40d
data_offload: Fix m_axis output stability issue
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Signed-off-by: David Winter <david.winter@analog.com>
2021-08-06 11:55:24 +03:00
2b55c7453b
data_offload: Fix duplicated output samples
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Signed-off-by: David Winter <david.winter@analog.com>
2021-08-06 11:55:24 +03:00
04f2d19d4b
data_offload: Fix data_offload getting stuck on oscillating m_saxis_ready
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Signed-off-by: David Winter <david.winter@analog.com>
2021-08-06 11:55:24 +03:00
0af50d3f72
data_offload: Fix oneshot mode
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Signed-off-by: David Winter <david.winter@analog.com>
2021-08-06 11:55:24 +03:00
66748510ea
data_offload: write_fsm: Always transition out of idle on high init_req
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Signed-off-by: David Winter <david.winter@analog.com>
2021-08-06 11:55:24 +03:00
9faef440b2
data_offload: Bump hdl version
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Signed-off-by: David Winter <david.winter@analog.com>
2021-08-06 11:55:24 +03:00
a89d0e6176
data_offload: Fix AXI register map
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Signed-off-by: David Winter <david.winter@analog.com>
2021-08-06 11:55:24 +03:00
537a284115
data_offload: Fix readme images
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Signed-off-by: David Winter <david.winter@analog.com>
2021-08-06 11:55:24 +03:00
6516b09a31
data_offload: Update README and generic block design
2021-08-06 11:55:24 +03:00
26518cdace
data_offload: Add block diagrams
2021-08-06 11:55:24 +03:00
9b1108ea87
data_offload: Flush the DMA if the transaction size is bigger than the storage
2021-08-06 11:55:24 +03:00
c82b0fb420
data_offload: Delete fifo_dst_rlast
2021-08-06 11:55:24 +03:00
0436a82f4e
data_offload: Fix alignment of write last beat and write full
2021-08-06 11:55:24 +03:00
378daf031c
data_offload: Improve timing in regmap
2021-08-06 11:55:24 +03:00
c27a0e4add
data_offload: Fix fifo_dst_ready generation
2021-08-06 11:55:24 +03:00
86b611c1f7
data_offload: Initial commit
2021-08-06 11:55:24 +03:00
6e97803437
ad_axis_inf_rx: Initialize output ports to avoid X propagation in simulation
2021-08-06 11:55:24 +03:00
b9ac3a78a9
interfaces: Add XFER_REQ to fifo_rd_rtl.xml
2021-08-06 11:55:24 +03:00
Laszlo Nagy
alin724
AndreiGrozav
Iulia Moldovan
LIacob106
Filip Gherman
David Winter
sergiu arpadi
Nicola Corna
Dan Hotoleanu
stefan.raus
Istvan Csomortani
Laszlo Nagy
Mihaita Nagy
Adrian Costina
Robin Getz
alin724