d2c99acae8
fmcomms2/TDD: Update synchronization interface
...
Synchronization is done by a simple req/ack interface between a master and slave terminal.
2015-08-06 15:14:36 +03:00
cfc4046821
fmcomms2: Add a synchronization interface for TDD mode.
...
Supported carrier are ZC706 and RFSOM.
The synchronization pulse is automatically generated by the master terminal, when TDD mode is enabled.
By default a terminal is slave, software must write 0x01 into TDD register 0x50.
2015-07-29 14:10:56 +03:00
8e631e56d6
fmcomms2: Add a synchronization interface for TDD mode.
...
Supported carrier are ZC706 and RFSOM.
The synchronization pulse is automatically generated by the master terminal, when TDD mode is enabled.
By default a terminal is slave, software must write 0x01 into TDD register 0x50.
2015-07-28 14:42:54 +03:00
36f71ea59b
fmcjesdadc1: common altera, fixed dmac configuration and connection. Connected reset for cpack
2015-07-28 12:33:24 +03:00
0422c87846
a5soc/base- remove hdmi, led/switchs to gpio
2015-07-27 12:08:33 -04:00
2ca2bf9383
a5soc- all hps clocks
2015-07-27 12:08:33 -04:00
e488ba0287
a5soc- remove hdmi core
2015-07-27 12:08:32 -04:00
0c5958091e
fmcjesdadc1/a5soc- base/fmc split
2015-07-27 12:08:32 -04:00
0a5dc938cd
fmcjesdadc1/a5soc- base/fmc split
2015-07-27 12:08:32 -04:00
f5f9ec38e8
a5soc- base/fmc split
2015-07-27 12:08:32 -04:00
58e0884ff9
a5soc- board qsys file
2015-07-27 12:08:32 -04:00
4d7ff0ed15
a5gte: Update ethernet connections
2015-07-27 16:05:26 +03:00
31ab81d627
a5gt: Updated ethernet clock constraints
2015-07-27 16:02:51 +03:00
797d679c72
fmcomms2: Updated c5soc project with the latest cores. Tested with Quartus 15.0
2015-07-24 16:43:33 +03:00
816238bb6c
fmcjesdadc:A5gt, decreased destination bus width for DMAs to 256. Increased DMA FIFO to 32
...
With lower buswidth, if all 4 channels are captured some samples are lost
With fifo size of 64, there are timing violations in the DMAC
With this configuration, 65536 samples could be captured from all 4 channels with no sample lost
Because of the DMAC destination bus is 256, the number of samples to be captured must be a multiple of 16, otherwise the system will freeze. This will be corrected in software
2015-07-24 15:31:19 +03:00
289e73660b
removed- xcvr is now part of qsys
2015-07-23 15:26:51 -04:00
fb648ab6f5
moved to qsys
2015-07-23 15:26:21 -04:00
3ccf1bef36
base system modifications
2015-07-23 15:23:10 -04:00
a1733238df
fmcjesdadc1- base/board split up
2015-07-23 15:21:53 -04:00
3ea60bca5d
fmcjesdadc1: a5gt, design working with quartus 15.0
...
- added cpack to the design
- removed 166 MHz clock as it is not needed. DMA destination is 512 bits
- removed clock bridge between DMA and DDR
2015-07-23 18:11:53 +03:00
d8e2196c75
fmcjesdadc1- board qsys
2015-07-22 15:44:04 -04:00
d66387f482
fmcjesdadc1- board qsys
2015-07-22 15:23:39 -04:00
3e2712cf18
a5gt-base: initial updates
2015-07-22 15:22:22 -04:00
64070b6f27
a5gt- base system
2015-07-22 15:04:59 -04:00
b325c0fc01
fmcomms2_zc702: Add SPI and GPIO interface for FREQCVT
2015-07-22 10:22:07 +03:00
28aea82952
fmcomms2_zc702: Add SPI and GPIO interface for FREQCVT
2015-07-22 10:16:04 +03:00
b4eac232db
a10gx- move cores inside qsys
2015-07-21 11:06:45 -04:00
fcc298d837
a10gx- move cores inside qsys
2015-07-21 11:06:17 -04:00
b3102b5095
daq2/a10gx-- xcvr+base changes
2015-07-21 11:01:45 -04:00
445c4c835d
daq2-bd: xcvr components
2015-07-21 10:54:23 -04:00
08e46c5ff2
a10gx-base: data-master connections
2015-07-21 10:53:54 -04:00
97b8468819
daq2- constraints
2015-07-20 09:32:17 -04:00
1d6a77049d
daq2- base/board split
2015-07-20 09:31:57 -04:00
4b8d764852
daq2- base system modifications
2015-07-20 09:31:44 -04:00
da2e7acacb
daq2- separate base/board systems
2015-07-20 09:31:15 -04:00
2f53dc4412
daq2- board system only
2015-07-20 09:30:32 -04:00
a87b8fbf94
a10gx- base system only
2015-07-20 09:29:30 -04:00
80dc3bf92f
daq2/a10gx: remove signal tap
2015-07-16 14:59:01 -04:00
1de74c0267
fmcadc4: Changed the SPI CS address similar to previous version
2015-07-16 18:22:05 +03:00
c949482574
fmcadc4: Set explicit PCORE_ID for AD9680
2015-07-16 18:21:49 +03:00
a7da779b94
Makefile: Updated Makefiles
2015-07-16 18:19:42 +03:00
4e99a2cb01
xcvr: remove signal tap
2015-07-16 08:09:56 -04:00
7c142178dd
daq2/a10gx- axi_jesd_xcvr sysref name changes
2015-07-15 15:59:52 -04:00
ffd767deb2
daq2/a10gx- axi_jesd_xcvr sysref name changes
2015-07-15 15:59:51 -04:00
6c0ad6ede8
daq3: bsplit/ccat -- removed
2015-07-15 13:05:53 -04:00
a454b73d27
fmcjesdadc1/a5gt: split xcvr cores
2015-07-15 09:44:53 -04:00
2d8fa2024b
fmcjesdadc1/a5gt: split xcvr cores
2015-07-15 09:44:52 -04:00
226e23ca1f
fmcjesdadc1- xcvr components
2015-07-15 09:44:51 -04:00
3b3fe4e642
fmcomms2/FREQCVT : Update GPIOs
...
Add gpio_muxout_[tx/rx] GPIO lines and update SPI interface I/Os for the FREQCVT board
2015-07-15 15:34:45 +03:00
1dcbf5e5a2
fmcomms2/zc706: Fix GPIO connections
...
Fix GPIO connections for the FREQCVT board.
2015-07-15 15:12:01 +03:00
1f7745610e
daq2- ddr updates
2015-07-14 12:46:52 -04:00
a38339a3ec
fmcomms2/rfsom: Add GPIO control for the RF card
2015-07-14 13:12:54 +03:00
ba2029a6e8
fmcomms2/rfsom: Delete trailing whitespaces from system_constr.xdc
2015-07-14 13:12:53 +03:00
a37932d881
fmcadc4: Changed the SPI CS address similar to previous version
2015-07-14 11:11:33 +03:00
a2e7fb9491
daq2/a10gx: qsys signal tap version
2015-07-13 10:07:18 -04:00
825fddd034
transceiver split up outside qsys
2015-07-10 11:45:07 -04:00
8c0d74aa90
transceiver split up outside qsys
2015-07-10 11:44:42 -04:00
e40aac9ab6
transceiver split up outside qsys
2015-07-10 11:44:22 -04:00
30ea87e60b
fmcadc4: Set explicit PCORE_ID for AD9680
2015-07-09 19:55:58 +03:00
897c31ebbf
imageon: moved spdif_rx to DMA3 to be compatible with both zc706 and zed
2015-07-09 10:58:54 +03:00
f1dd2435b4
signal tap removed
2015-07-08 15:47:31 -04:00
c9e73b023d
signal tap removed
2015-07-08 15:46:52 -04:00
f64df40a0a
signal tap removed
2015-07-08 15:47:50 -04:00
19bf05c740
signal tap removed
2015-07-08 15:47:48 -04:00
c972779217
motcon2_fmc: updated util_gmii_to_rgmii and motcon2_fmc project for improved performance of the ethernet
...
- removed the delay controller from the top file and added it inside the util_gmii_to_rgmii core
- removed delay related xdc constraints as they are not needed
2015-07-08 16:23:33 +03:00
bbf1c5b803
transceiver core added/gpio removed
2015-07-07 15:30:38 -04:00
075b1e5424
daq2/a10gx: added axi_jesd_xcvr control
2015-07-07 10:22:36 -04:00
46fa91d5be
Makefile: Update Make files
2015-07-03 18:08:57 +03:00
8c98399c37
imageon_ZC706: Add axi_spdif_rx core to the design
2015-07-03 17:48:29 +03:00
27b786e92f
imageon_loopback: Use BUFIO for the HDMI clock buffer
...
Since we are just doing a loopback all the logic is contained within the
IO bank. By using a BUFIO instead of a BUFG we avoid having to route the
clock signal from the IO bank to the middle of the FPGA and back to the IO
bank. This reduces the skew between clock and the data signals and makes
sure that the we can use the same design over a range of different
resolutions without having to calibrate the delay.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-07-03 15:07:17 +02:00
02b5ce82ad
imageon_loopback: Invert transmit clock
...
The ADV7511 samples on the rising edge. Update the data on the falling
edge, this gives us a larger margin and improved signal stability.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-07-03 15:07:17 +02:00
281cab091c
imageon_loopback: Create a clock for hdmi_rx_clock
...
Create a clock for the HDMI clock to make sure that the timing paths are
properly constraint.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-07-03 15:07:17 +02:00
5b2877b66f
imageon_loopback: Use BUFIO for the HDMI clock buffer
...
Since we are just doing a loopback all the logic is contained within the
IO bank. By using a BUFIO instead of a BUFG we avoid having to route the
clock signal from the IO bank to the middle of the FPGA and back to the IO
bank. This reduces the skew between clock and the data signals and makes
sure that the we can use the same design over a range of different
resolutions without having to calibrate the delay.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-07-03 15:06:03 +02:00
f5fc3a4d2f
imageon_loopback: Invert transmit clock
...
The ADV7511 samples on the rising edge. Update the data on the falling
edge, this gives us a larger margin and improved signal stability.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-07-03 15:06:03 +02:00
10cc007c57
imageon_loopback: Create a clock for hdmi_rx_clock
...
Create a clock for the HDMI clock to make sure that the timing paths are
properly constraint.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-07-03 15:06:03 +02:00
95500d4022
fmcomms2_rfsom: Fix GPIO connections
2015-07-03 13:03:19 +03:00
32ae7c771a
fmcomms2_ALL: Add/fix ENABLE/TXNRX control
...
Add ENABLE/TXNRX control for TDD, and preserve backward compatibility for pin control with GPIOs
2015-07-03 12:55:37 +03:00
5208ebedd5
Revert "fmcomms2_ALL: Preserve backward compatibility for ENABLE/TXNRX control"
...
This reverts commit 6b15704b70
2015-07-03 10:20:50 +03:00
88f936cc86
imageon: Put HDMI input/output FF into the IOB
...
This gives us predictable delays as well as very small skew between the induvidual data lines.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-07-02 18:36:51 +02:00
94d1792aba
Revert "imageon: Connect raw data to ILA"
...
This reverts commit 9e4fb2d048
2015-07-02 18:36:51 +02:00
eb3a0c179b
imageon: Put HDMI input/output FF into the IOB
...
This gives us predictable delays as well as very small skew between the induvidual data lines.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-07-02 18:33:32 +02:00
e269fe1dd0
Revert "imageon: Connect raw data to ILA"
...
This reverts commit 9e4fb2d048
2015-07-02 18:33:32 +02:00
18e8914087
fmcjesdadc1/a5gt: pn-errors version
2015-07-01 13:43:12 -04:00
35aca98b5f
fmcjesdadc1/stap: added
2015-07-01 13:43:10 -04:00
68cb6df366
imageon: Connect raw data to ILA
...
Connect the raw HDMI data as generated by the ADV7604 to the ILA. For
debugging it is quite useful to be able to compare the data before and
after conversion pipeline.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-07-01 18:43:51 +02:00
c8a095f79c
imageon: Increase ILA buffer size
...
2048 samples is not even enough for one 1080p line. Increase it to 4096.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-07-01 18:43:51 +02:00
cb18b2c0fd
imageon: Fix HDMI RX DMA data ILA probe width
...
The DMA data output of the HDMI RX core is 64-bit wide.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-07-01 18:43:51 +02:00
c372064302
Add .gitattributes file
...
Add .gitattributes file which sets up the eol encoding handling. This will
make sure that we get a uniform eol encoding across different operating
systems.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-07-01 18:43:51 +02:00
6b15704b70
fmcomms2_ALL: Preserve backward compatibility for ENABLE/TXNRX control
...
By default the ENABLE/TXNRX pins are controlled by GPIOs, if the TDD module is enabled, the TDD FSM will take over the control of these two pins.
2015-07-01 15:26:46 +03:00
0102e3e02c
fmcomms2_ALL: Preserve backward compatibility for ENABLE/TXNRX control
...
By default the ENABLE/TXNRX pins are controlled by GPIOs, if the TDD module is enabled, the TDD FSM will take over the control of these two pins.
2015-07-01 13:54:01 +03:00
9e4fb2d048
imageon: Connect raw data to ILA
...
Connect the raw HDMI data as generated by the ADV7604 to the ILA. For
debugging it is quite useful to be able to compare the data before and
after conversion pipeline.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-30 18:03:03 +02:00
e429cb3f5c
imageon: Increase ILA buffer size
...
2048 samples is not even enough for one 1080p line. Increase it to 4096.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-30 18:02:44 +02:00
bcd12c8ead
imageon: Fix HDMI RX DMA data ILA probe width
...
The DMA data output of the HDMI RX core is 64-bit wide.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-30 18:02:44 +02:00
330c205e8e
fmcjesdadc1- sys_clk changes
2015-06-30 10:47:21 -04:00
6bc24e25eb
stap- need to be qsys
2015-06-29 13:26:32 -04:00
d25e02d7ee
stap- need to be qsys
2015-06-29 13:26:20 -04:00
499357a65a
motcon2_fmc: Updated project to include XADC
...
- connected reset pin, as vivado reports the reset pin erroneously
- configured XADC in simultaneous sampling mode from XAUX0 and XAUX8
- connected XADC interrupt
- because in the project constraints some base pin constraints are overwritten, the project constraints are processed late
- GPI pins were assigned instead of the XADC GIO0 and GIO1, which were assigned to the XADC for external mux mode
- removed commented code
2015-06-29 16:56:25 +03:00
f32039f154
imageon: Hdmi_iic_rstn is accessible through a GPIO.
...
Connect hdmi_iic_rstn to GPIO[33]
2015-06-29 10:49:59 +03:00
aef6f6b20b
imageon: Hdmi_iic_rstn is accessible through a GPIO.
...
Connect hdmi_iic_rstn to GPIO[33]
2015-06-29 10:48:57 +03:00
6862655b0d
Add .gitattributes file
...
Add .gitattributes file which sets up the eol encoding handling. This will
make sure that we get a uniform eol encoding across different operating
systems.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-26 11:07:10 +02:00
fcc185d769
Makefile: Updated makefiles
...
- removed up_drp_control, up_delay_control dependencies where not needed
- added axi_jesd_gt core in the library makefile
- fixed timing tcl dependency for altera projects
2015-06-25 14:59:34 +03:00
543e08b67a
fmcadc1: sdc updates
2015-06-25 04:25:39 -04:00
15740a7d34
fmcjesdadc1- 15.0 updates
2015-06-24 05:31:09 -04:00
714d415804
daq2/a10gx- signaltap changes
2015-06-19 14:33:04 -04:00
51e6a74a3d
daq2/a10gx- add xmit swap
2015-06-19 14:32:59 -04:00
d6b1260678
daq2/a10gx- signal tap + gpio
2015-06-19 14:32:58 -04:00
67df6b3ea8
a10gx- disable lab cell on dsp input register
2015-06-19 14:32:54 -04:00
db76fe3298
tquest- generate the timing report file
2015-06-19 14:32:53 -04:00
c3ea99d1f8
fmcadc2: Fixed zc706 spi connection
2015-06-19 13:31:59 +03:00
9fa705c488
fmcadc2: Fixed zc706 spi connection
2015-06-19 13:13:02 +03:00
301226c766
fmcjesdadc1: Fixed mdc_mdio connection for kc705
2015-06-18 11:06:47 +03:00
f01ba54c5f
fmcomms1: Fixed mdc_mdio connection for kc705
2015-06-18 11:06:33 +03:00
009d33f0a0
ad9467: Fixed mdc_mdio connection for kc705
2015-06-18 11:06:20 +03:00
41799c55dc
fmcjesdadc1: Fixed mdc_mdio connection for kc705
2015-06-18 11:04:29 +03:00
6de154d2c2
fmcomms1: Fixed mdc_mdio connection for kc705
2015-06-18 11:04:00 +03:00
988f4fac8f
ad9467: Fixed mdc_mdio connection for kc705
2015-06-18 11:03:11 +03:00
e6d9735e54
fmcomms1: Fixed zed top file, the DAC dma was not correctly connected
2015-06-17 14:43:34 +03:00
2e46bda916
motcon2_fmc: Update project to use the latest util_gmii_to_rgmii
2015-06-16 17:43:10 +03:00
8fc0e0e62d
fmcjesdadc1: Fixed vc707 ethernet connections
2015-06-16 16:27:09 +03:00
142f802f54
adv7511: Fixed vc707 ethernet connections
2015-06-16 16:26:58 +03:00
a2f380ab64
fmcjesdadc1: Fixed vc707 ethernet connections
2015-06-16 15:31:17 +03:00
98ae6d567f
adv7511: Fixed vc707 ethernet connections
2015-06-16 15:30:47 +03:00
4c80013faf
projects/daq2: gt lane split
2015-06-12 15:56:03 -04:00
e6525136a9
daq2/common: axi_ad9144_fifo needs a proper reset sequence
...
Connect the axi_ad9144_fifo/dma_rst signal to sys_cpu_reset
2015-06-12 14:03:46 +03:00
f587aa42d9
a10gx- tx sync
2015-06-10 14:32:25 -04:00
e3e4af5c51
daq2/zc706: open ports
2015-06-10 14:25:58 -04:00
97ab5e0ef7
fmcomms1: Update project to integrate the new util_wfifo
2015-06-10 15:16:17 +03:00
3d86f140e5
usdrx1: Removed ILA as the ports from axi_jesd_gt were removed
2015-06-10 10:56:55 +03:00
1fcdeac054
fmcjesdadc1/common: The new GT module does not have integrated monitor/debug ports
2015-06-09 11:50:55 +03:00
2330d1e27d
daq1/common: The new GT module does not have integrated monitor/debug ports
2015-06-09 11:50:27 +03:00
00b8c171b8
a10gx: pll locked to reset controller
2015-06-08 15:00:11 -04:00
be6d6f627a
ad9265: Removed ILA
2015-06-08 15:03:34 +03:00
25e56a4d03
arradio: renamed fmcomms2 c5soc to arradio
2015-06-08 11:35:21 +03:00
dc7064ab95
fmcomms2/vc707 - wfifo changes
2015-06-05 12:44:04 -04:00
25f1ad73f0
fmcomms2/freqcvt: Update SPI interface I/O
2015-06-05 18:16:14 +03:00
f1e75963a2
fmcomms2: wfifo+pack changes
2015-06-05 09:20:50 -04:00
47469ad375
ad9434/ad9467 : Connect reset signal for AXI streaming interface of the device dma
2015-06-04 18:09:48 +03:00
3b1ea7e528
axi_ad9361/tdd: Cherry picked commit 598ece4 from hdl_2015_r1 branch
...
598ece4c8d
2015-06-04 18:09:47 +03:00
a8a71b4971
alt-tq: common file
2015-06-04 11:00:25 -04:00
f81d22a17a
altera- common timing check
2015-06-04 10:56:32 -04:00
d111692608
daq2/a10gx- ddr-ref @133
2015-06-04 10:53:16 -04:00
886c24f597
tq-alt: added
2015-06-04 10:53:14 -04:00
264dbfed35
common: rfsom: Add constraints for the eth1 rx clock
...
Add clock rate constraints for the eth1 rx clock, otherwise the tools
assume the RX paths are unconstrained and creates a bitstream which
violates hold times which causes bit errors on the RX path.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-03 17:21:43 +02:00
71b5004b25
projects- drp moved to up-clock domain
2015-06-01 14:57:59 -04:00
f9ffaf457d
projects/daq2- drp moved to up clock
2015-06-01 13:39:26 -04:00
4a701d3895
a10gx- no-ddr
2015-06-01 11:00:02 -04:00
aa24c442f5
a10gx- no-ddr
2015-06-01 11:00:01 -04:00
5250635162
cn0363: Fix ad_iobuf signal names
...
The signal names for the ad_iobuf were recently changed, adjust the cn0363
project accordingly.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-05-27 13:25:19 +02:00
73d7bc111e
cn0363: Add missing Makefiles
...
Those were accidentally overlooked during the initial commit of the project.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-05-26 18:44:24 +02:00
77eff35d67
motcon2_fmc: Fixed constraint for renamed port
2015-05-23 19:02:48 +03:00
29ca9e4b8c
vc707: common, fixed address range for flash
2015-05-23 00:14:08 +03:00
8bd5fa5802
kc705: Common, fixed address range for the flash. Changed the start address so that it won't interfere with other cores
2015-05-23 00:10:06 +03:00
f91fbf1bc1
ad9434_zc706: Fix SPI interface
2015-05-22 12:31:48 +03:00
a6cae6b477
iobuf: do is a system verilog keyword
2015-05-21 14:06:17 -04:00
ad3198f623
a10gx: top level fixes
2015-05-21 14:06:15 -04:00
c9832d2f84
Remove ad7175_zed project
...
This project has been superseded by the cn0363 project and can be removed.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-05-21 17:21:35 +02:00
c53f8c15ee
Add CN0363 project
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Add support for the CN0363 (colorimeter) board connected to the ZED board.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-05-21 17:21:35 +02:00
6b9906b22b
Refresh Makefiles
...
Re-generate the Makefiles after a small update to the generation script:
- Entries are sorted alphabetically
- Empty dependency lines are skipped
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-05-21 14:21:54 +02:00
ebbc0c6ed5
fmcomms5: zc706, removed debug related ila, as the pins were removed from the AD9361 IP
2015-05-21 14:19:22 +03:00
a047d3990a
fmcadc2_vc707: Fix interrupts
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+ Remove some trailing whitespaces
+ Fix interrupt connections
2015-05-21 11:03:16 +03:00
19b094cab5
daq2/a10gx- added jesd align
2015-05-20 15:39:27 -04:00
f1c30ac225
daq2/a10gx- qsys updates
2015-05-20 14:24:49 -04:00
4927ca85c2
projects- jesd-align port name change
2015-05-20 14:24:26 -04:00
52b6077a46
a10gx- 15.0 updates
2015-05-19 15:12:23 -04:00
0805da3b6b
fmcomms2/rfsom- enable dac delay
2015-05-18 16:45:54 -04:00
3e51d29f75
enable/txnrx- tdd changes
2015-05-18 14:28:20 -04:00
c19749361d
Makefiles: Updated makefiles to have as a result the programming file instead of the project file.
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Also fixed altera projects dependencies
2015-05-18 17:22:46 +03:00
672a5a4dfa
a10gx- updates
2015-05-14 14:35:43 -04:00
b311b9dac6
a10gx- updates
2015-05-14 14:35:42 -04:00
3226ca4374
fmcadc4- ad9680 version
2015-05-11 13:55:02 -04:00
c28ff2ff9a
fmcadc4- ad9680 version
2015-05-11 13:55:02 -04:00
16541335e6
fmcadc4- ad9680 version
2015-05-11 13:55:02 -04:00
2cd1d8a591
fmcadc4- ad9680 version
2015-05-11 13:55:02 -04:00
0a6efaccca
fmcadc4- ad9680 version
2015-05-11 13:55:02 -04:00
848dac70d5
a10gx: updates--
2015-05-11 11:56:27 -04:00
dc0eea5f0f
a10gx: updates--
2015-05-11 11:56:26 -04:00
bdc3f3d807
a10gx: updates--
2015-05-11 11:56:24 -04:00
75e055dab9
daq2/a10gx- initial commit
2015-05-11 11:56:23 -04:00
515dfd88d4
a10gx- added
2015-05-11 11:56:22 -04:00
14b721682d
motcon1_fmc: Removed
2015-05-11 18:02:52 +03:00
3d4e9eb36a
ac701: common, commit ethernet reset pin
2015-05-11 16:41:28 +03:00
15618c9edf
daq2 : Integrate the DACFIFO into the supported projects.
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+ All pack/unpack logic is made by the cpack and upack modules.
+ The DAC FIFO is integrated between the TX DMA and cpack.
+ All the top files are updated, all the projects compiled successfully.
2015-05-11 12:20:50 +03:00
bad821ba1c
sys_dmafifo: Update the p_sys_dacfifo process
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Update the ports and parameters at util_dacfifo instantiation.
2015-05-11 12:20:47 +03:00
d9a124b767
fmcomms2_zc706: TDD integration, initial commit.
2015-05-11 12:20:45 +03:00
00335a2af2
Makefile: Fix ZC706 Makefiles with propper address for the mig file
2015-05-11 10:25:07 +03:00
81a20b4abb
rfsom- apisys lb updates
2015-05-08 15:22:17 -04:00
d515ab1b61
adv7511: AC701, update project to work at full HD resolution
2015-05-08 18:53:47 +03:00
293ec6a319
fmcomms2: c5soc project updated to 14.1
2015-05-08 17:44:16 +03:00
91279253ef
Makefiles: Added mig project file as a dependency for Microblaze based projects. Also updated usdrx1 a5gt Makefile
2015-05-08 15:31:40 +03:00
573acc8af6
usdrx1: A5GT project updated to 14.1
2015-05-08 15:04:44 +03:00
1c9b41db6f
fmcjesdadc1: A5GT project, added modular sgdma for Ethernet, nios configured for linux
2015-05-08 14:51:24 +03:00
68570c1815
vc707: Common system mig, updated datawidth to 256 from 128
2015-05-08 10:51:27 +03:00
d7a0f1ffe3
projects/imageon_loopback: Add the option of setting hdmi_iic_rstn externally.
2015-05-07 15:17:16 +03:00
949abcdc8f
Makefile: Updated makefiles so that the project recipe does not depend on lib
2015-05-06 14:58:29 +03:00
4f75414a1a
fmcomms1: Removed constraints that are not needed
2015-05-05 23:39:08 +03:00
1fcaf8fb63
fmcomms1: Updated AC701 project to meet timing. Reduced FIFO size for AD9643 DMA to 8
2015-05-05 23:37:01 +03:00
90a5bb81b6
cftl_cip: Updated project to work with the new util_pmod_adc core
2015-05-05 23:34:52 +03:00
95805f21fa
adv7511: Fixed system_top for mitx045 board
2015-05-05 10:08:11 +03:00
3517b6941c
adv7511:kcu105, axi_hdmi_tx, axi_spdif_tx constraints modified so they apply to ultrascale
2015-05-05 10:06:26 +03:00
319f821fab
zc706pr - makefile
2015-05-04 13:41:03 -04:00
ab85e2ba36
zc706pr - 706 partial reconfiguration
2015-05-04 12:36:57 -04:00
e489090fbb
scripts- initialize prcfg list
2015-05-04 12:34:19 -04:00
2a8703763e
zc706pr - 706 partial reconfiguration
2015-05-04 12:33:28 -04:00
c3dd9258e7
zc706: project mode
2015-05-04 10:25:12 -04:00
62acd37fee
zc706: project mode
2015-05-04 10:25:07 -04:00
e7a0da9089
fmcomms2 : Verify the existence of the PR license
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The fmcomms2 runs by default on PR mode, if the project script does not find a PR license, will implement just the default mode.
2015-05-04 15:12:38 +03:00
4bb26caa13
itx045: default install
2015-05-01 16:19:10 -04:00
ad551a0073
itx045: updates
2015-05-01 16:18:43 -04:00
aced144916
itx045: updates
2015-05-01 16:18:23 -04:00
ff443655ca
itx045: add ps7 settings
2015-05-01 16:17:59 -04:00
26fb85583b
adi_project- prefix directory for gitignore & make clean
2015-05-01 13:18:12 -04:00
00cafd4df0
fmcomms2/zc706: add partial reconfiguration
2015-05-01 12:23:18 -04:00
3641d8f714
fmcomms2/zc706: add partial reconfiguration
2015-05-01 12:23:11 -04:00
75a81d67d8
fmcomms2/zc706: add partial reconfiguration
2015-05-01 12:23:07 -04:00
0dc4c9cda9
adi_project: added partial reconfiguration
2015-05-01 12:21:59 -04:00
140c622c8b
prcfg: common files
2015-05-01 11:48:09 -04:00
a8d4c916c1
fmcomms2_bd: remove axi3 switch
2015-05-01 11:47:29 -04:00
3b58785368
daq1: Updated jesd reset connection. Fixed dmac async configuration. Updated zc706 constraints
2015-04-30 12:14:03 +03:00
e332fa01c8
ad6676evb, daq2, fmcadc2, fmcjesdadc1, usdrx1: Updated jesd reset connection
2015-04-30 12:11:46 +03:00
1df48a2e6e
Add hdmiio_int pin.
2015-04-29 18:50:28 +03:00
19ef85cec3
vc707: Changed mig project to use BANK_ROW_COLUMN, as it seems this mode gives best performance
2015-04-28 17:15:58 +03:00
288b9cccff
Makefile: Added makefiles for imageon_loopback project. Updated axi_ad9152, util_gmii_to_rgmii, util_wfifo to include constraints file
2015-04-28 15:22:37 +03:00
252aa135eb
ad9739a: Changed dma and interconnect clock to 200mhz. Removed div_clk constraint, as it is autodetected
2015-04-28 15:14:31 +03:00
3fdda617a4
fmcomms1: updated common, changed DMAC fifo size and wfifo reset signal source
...
- changed DMAC FIFO size to 16, as it should be large enough
- connected wfifo reset to adc_rst from axi_ad9643 core
2015-04-28 14:58:04 +03:00
37bfb2ef4b
ad9265: Updated common, wfifo is reset by the adc_rst signal from axi_ad9265 core
2015-04-28 14:53:12 +03:00
1eebfd3155
projects/imageon_loopback: Initial commit.
2015-04-28 10:32:28 +03:00
e51edfbadb
adv7511: KC705 mdio pin name fix
2015-04-27 11:21:36 +03:00
7e6f2bfa15
ad9265: Updated constraints file.
2015-04-27 11:20:42 +03:00
272148eee5
rfsom: sdio 50mhz
2015-04-23 15:30:50 -04:00
7611c2ae17
kcu105: ddr mig rbc to rcb
2015-04-23 15:30:48 -04:00
bb185296d7
fmcadc2_vc707: Increase the BRAM FIFO size to its maximum: it can store 1M samples.
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The 2^18 dma address width with a 64 dma data width will result a FIFO, what will be implemented by 512 RAMB36 cells.
This is a the maximum BRAM FIFO depth in case of the VC707.
2015-04-23 18:00:00 +03:00
f232a36141
common: Place HDMI interface registers into the IOB
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The paths from the HDMI interface registers to the IO pads are
unconstrained. This means the P&R can in theory put the register anywhere
which could lead to stability issues on the interface, depending on what
else is in the fabric. To get predictable delays for the register to IO pad
path place the register into the IOB section.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-23 14:33:47 +02:00
bd6c76f4ab
fmcomms5: Set DMA AXI type to AXI3 on ZYNQ
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The HP memory ports on ZYNQ are AXI3. The AXI-DMAC supports both native AXI3
and AXI4, by configuring it for AXI3 there is no need for a protocol
converter inside the interconnect, that connects the DMAC to the HP port.
In addition to that also set the data width for the DMAC on the HP port side
to 64 so there is no need for a memory width converter in the interconnect.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-23 14:33:47 +02:00
4ed7c9aee9
fmcomms2_pr: zc706: Fix ddr and fixed_io signal names
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The toplevel input/output signal names are lower case, but the signals
connected to the system_wrapper are upper case. Since verilog is case
sensitive this leaves the toplevel input/output signals unconnected. Fix
this by using lower case names everywhere.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-23 14:33:47 +02:00
558f2e89af
imageon: zc706: Fix ddr and fixed_io signal names
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The toplevel input/output signal names are lower case, but the signals
connected to the system_wrapper are upper case. Since verilog is case
sensitive this leaves the toplevel input/output signals unconnected. Fix
this by using lower case names everywhere.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-23 14:33:47 +02:00
1bb5b6e55f
adv7511: zc706: Fix ddr and fixed_io signal names
...
The toplevel input/output signal names are lower case, but the signals
connected to the system_wrapper are upper case. Since verilog is case
sensitive this leaves the toplevel input/output signals unconnected. Fix
this by using lower case names everywhere.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-23 14:33:47 +02:00
a61a195e3f
Makefiles: Updated makefiles to add the new constraints as dependecies
2015-04-23 11:16:39 +03:00
e25cfb9d9f
rfsom: ddr configuration
2015-04-22 13:45:11 -04:00
a100ecd308
util_dacfifo: Update BRAM DAC Fifo
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The fifo will be placed between the DMAC and the Upack module, all the interfaces were updated.
2015-04-21 15:45:56 +03:00
3fd830b038
fmcomms2: Use AXI3 interface for the DMA on ZYNQ
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On ZYNQ the HP interconnects have a AXI3 interface. The DMA controller
supports both AXI4 and AXI3. By switching to AXI3 there is no need to create
a protocol converter between the DMA and the HP port.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-17 19:51:37 +02:00
71d4f3a474
fmcomms2: Don't mark synchronous paths as asynchronous for the DMAs
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The AXI master interface and the register map AXI slave interface use the
same clock. No need to mark the interfaces as asynchronous. This removes the
need for CDC logic on those paths.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-17 19:51:37 +02:00
dc2b37bd0c
Makefile: Added top level Makefile. Modified behavior of clean and clean-all
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Clean ran for a project will clean only the project files.
Clean-all ran for a project will clean also the library files on which the project depends.
The clean commands will only remove specific files and directories.
The top Makefile allows several options(per suggestion from jameyhicks):
make fmcomms1.zed will run "make all" in projects/fmcomms1/zed/
make clean will run "make clean" for all the projects
make clean-all will run "make clean" for all the projects and libraries
make lib will run "make all" for the library files
2015-04-17 17:22:38 +03:00
374f82e7de
makefiles: The clean command for library won't remove the xml files, except for component.xml.
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Updated also the dmac dependencies
2015-04-16 11:53:27 +03:00
8b5d1a8693
fmcadc2: Connect the second CS line for the external SPI interface
2015-04-15 19:08:17 +03:00
780455d68c
Makefile: Updated makefiles. Added makefiles for altera
2015-04-09 17:57:06 +03:00
afea42f444
rfsom: Use interface connection for the I2S stream
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Use a interface connection for the I2S stream instead of individually
connecting each of the signals. This make things a bit cleaner.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-08 13:29:26 +02:00
90e132d203
mitx045: Use interface connection for the I2S stream
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Use a interface connection for the I2S stream instead of individually
connecting each of the signals. This make things a bit cleaner.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-08 13:29:25 +02:00
7f26bfe436
zed: Use interface connection for the I2S stream
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Use a interface connection for the I2S stream instead of individually
connecting each of the signals. This make things a bit cleaner.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-08 13:29:25 +02:00
06e37b0082
common: zed: Use interface to connect I2C core to the I2C mixer
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Use a interface connection for the I2C connection instead of individually
connecting each of the signals. This make things a bit cleaner.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-08 13:29:25 +02:00
7da59a435f
common: rfsom: Use interface connection for the HDMI DMA stream
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Use a interface connection for the HDMI DMA stream instead of individually
connecting each of the signals. This make things a bit cleaner.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-08 13:29:25 +02:00
Istvan Csomortani
Adrian Costina
Rejeesh Kutty
Lars-Peter Clausen
dbogdan