The MMCM generating the logic analyzer clock unfortunately consumes a
disproportionately large amount of power compared to the rest of the
design.
Replace it by sourcing the logic analyzer clock from one of the Zynq FCLKs.
The IO PLL is running anyway so the power requirement is much lower.
For the time being this means we loose the ability to source the clock from
an external pin. But that feature is not supported by software at the
moment anyway. We'll bring it eventually when required.
This changes reduces power consumption by roughly 100mW.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Use the new axi_rd_wr_combiner module to ... the read and write DMA
interfaces into a single interface. This allows the AXI interconnect
completely optimize itself away and reduce the overall resource utilization
of the project.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Lars-Peter Clausen
Adrian Costina
Rejeesh Kutty