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63 Commits (b20714bae2eb1bd64044778488b673ac4d10b265)

Author SHA1 Message Date
Rejeesh Kutty f3c9627cae adi_project: demote reset warnings to info 2014-10-17 14:38:13 -04:00
Rejeesh Kutty 0aed11fa6c adi_project: demote useless warnings 2014-10-15 14:50:54 -04:00
Istvan Csomortani f2cd7626f5 adi_project : ZC706 board name changed on 2014.2 2014-09-22 17:33:49 +03:00
Rejeesh Kutty 57bb3705f2 zc706-plddr3: read changes to lower dma clock 2014-06-25 09:20:58 -04:00
Adrian Costina c52327d0c6 common,adv7511: Added mitx045 platform. 2014-06-02 11:08:03 +03:00
Rejeesh Kutty 51c0ee1e20 ml605: tcl updates 2014-05-06 09:29:21 -04:00
Rejeesh Kutty ef60cce15e kcu105: added 2014-04-30 14:41:40 -04:00
Istvan Csomortani 5b0e37b97a adi_project.tcl : Modify implementation strategy 
- Change implementation strategy to Performance Explore.
	  At some projects, this could prevent timing issues, it not
	  increase the overall implementation time in a dramatic way.
 2014-04-07 15:02:38 +03:00
Adrian Costina 698e9f4757 Added phys_opt_design step for fixing timing 
The FMCOMMS1 meets timing on ZED/ZC702 only if the phys_opt_design step
is part of the implmentation flow, with the Explore argument.
"This step performs physical optimizations such as timing-driven
replicaiton of high fanouts nets to improve timing results"
 2014-03-19 16:42:44 +02:00
Rejeesh Kutty f3ae57a53e global clock and reset names 2014-03-11 09:57:59 -04:00
Istvan Csomortani 793bf2f350 Change the adi_project_run process to prevent "const_type UCF" issue 
- Set the constraint type to XDC before run the synthesis
 2014-03-07 11:06:11 +02:00
Rejeesh Kutty 350ec5e633 changed path settings 2014-03-03 10:06:36 -05:00
Rejeesh Kutty ddac1a8834 added common board files 2014-02-28 21:17:01 -05:00