a881557645
base_design: Fixed AC701 and VC707 contstraints
...
AC701: Modified the IOSTANDARD for some of the pins to correspond to the
AC701 user guide.
VC707: Fixed naming for some system clocks
2014-03-31 17:38:20 +03:00
0f10623be4
AC701/VC707: Define common variables
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Define variables sys_zynq, sys_mem_size, sys_addr_cntrl_space.
2014-03-25 14:24:51 +02:00
aa7b0bb4dd
VC707 basesys: General fixes, actual status: working
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- Add an auxiliary cpu interconnect
- Add an auxiliary interrupt concatenation module
- Add new MIG file, current frequency of the DDR interface is 100
Mhz
- Memory interconnect optimisation strategy is 'Maximize
Performance'
2014-03-24 13:07:48 +02:00
75963ab376
Initial check in of VC707 base project
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- All source files for the VC707 base project
- Update the common base system to the new naming convention
2014-03-10 17:26:17 +02:00
ddac1a8834
added common board files
2014-02-28 21:17:01 -05:00
Adrian Costina
Istvan Csomortani
Rejeesh Kutty