Commit Graph

9 Commits (b21fb3a0e0d9a59d37970d4e0c2145a61ca72f10)

Author SHA1 Message Date
laurent-19 2ae09c9808 Check guidelines. Remove redundancies
* Removed empty/commented lines
 * Regenerated Makefiles
 * Removed redundancies adc channels data width
 * Set data width 32-bit: max resolution and CRC header

Signed-off-by: laurent-19 <laurentiu.popa@analog.com>
2023-03-29 15:08:07 +03:00
Sergiu Arpadi 445cca61ef SPI Engine: Update spi_engine.tcl
The SPI Engine cores were named directly inside the script and this
would mean that for multiple SPI Engine instances IPs with the same
name would appear. These updates will introduce the hierarchy name
into the name given to the cores and will therefore allow for
multiple instances of SPI Engine to be added to the same Xilinx
project.

Projects which use spi_engine.tcl will be updated to account for
these changes.
2023-03-29 15:08:07 +03:00
Iulia Moldovan db94628cc6 library & projects: Update Makefiles
Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
2023-01-27 11:54:05 +02:00
Bogdan Luncan 72313df81f Updated the makefiles to build the projects in subdirectories based on the build parameters.
Running 'make' will build the default project directly in the project folder (like it did before)
Running 'make RX_LANE_RATE=15 TX_LANE_RATE=15' will build the project inside the 'RXRATE15_TXRATE15' subdirectory.
Running 'make CFG=cfg/test_config.txt" will use the variables found inside the configuration file and build the project inside the 'test_config' subdirectory.
Running 'make clean' will clean the default project only.
Running 'make CFG=cfg/test_config.txt clean' will clean the 'testconfig' build.
Running 'make clean-all' will delete all the built configurations and libraries.

Note that the 'JESD' and 'LANE' words from the parameter names are stripped.

Signed-off-by: Bogdan Luncan <bogdan.luncan@analog.com>
2022-11-14 09:38:42 +02:00
PopPaul2021 9caa15522a
The memory interconnect was moved from HP0 to HP1 on Coraz7s projects (#1023) 2022-09-29 15:14:57 +03:00
PopPaul2021 8a77d4fb05
coraz7s: Memory interconnect fix (#1014) 2022-09-23 14:58:43 +03:00
Iacob_Liviu 482f0489a3 scripts: Merge adi_env.tcl into a single file
Move the new adi_env.tcl file from hdl/projects/scripts into hdl/scrips
2022-08-08 13:52:54 +03:00
Iulia Moldovan 961ebe0cc2 projects: Update .v files according to guideline
Deleted lines after endmodule and consecutive empty lines.
Modified parentheses, extra spaces.
Fixed indentation.
Fixed parameters list to be each parameter on its line.

Signed-off-by: Iulia Moldovan <iulia.moldovan@analog.com>
2022-06-28 18:06:56 +03:00
Stanca Pop c2d37b2db3 pulsar_adc_pmdz: Initial commit 2021-11-22 13:39:17 +02:00