Commit Graph

5 Commits (b21fb3a0e0d9a59d37970d4e0c2145a61ca72f10)

Author SHA1 Message Date
laurent-19 2ae09c9808 Check guidelines. Remove redundancies
* Removed empty/commented lines
 * Regenerated Makefiles
 * Removed redundancies adc channels data width
 * Set data width 32-bit: max resolution and CRC header

Signed-off-by: laurent-19 <laurentiu.popa@analog.com>
2023-03-29 15:08:07 +03:00
Sergiu Arpadi 445cca61ef SPI Engine: Update spi_engine.tcl
The SPI Engine cores were named directly inside the script and this
would mean that for multiple SPI Engine instances IPs with the same
name would appear. These updates will introduce the hierarchy name
into the name given to the cores and will therefore allow for
multiple instances of SPI Engine to be added to the same Xilinx
project.

Projects which use spi_engine.tcl will be updated to account for
these changes.
2023-03-29 15:08:07 +03:00
PopPaul2021 9caa15522a
The memory interconnect was moved from HP0 to HP1 on Coraz7s projects (#1023) 2022-09-29 15:14:57 +03:00
PopPaul2021 8a77d4fb05
coraz7s: Memory interconnect fix (#1014) 2022-09-23 14:58:43 +03:00
Stanca Pop c2d37b2db3 pulsar_adc_pmdz: Initial commit 2021-11-22 13:39:17 +02:00