Commit Graph

2370 Commits (b2550b7aa09fc48b4c146a5c0e28c44788ef0966)

Author SHA1 Message Date
Rejeesh Kutty b85a282748 fmcomms11- lane swap 2016-11-16 10:26:47 -05:00
István Csomortáni bdd14c3874 README: Delete second rule under headers
By default there is a rule under each header, no need for another one.
2016-11-16 11:04:43 +02:00
István Csomortáni 81e47edcd5 README: Set links for documentation 2016-11-16 10:57:39 +02:00
rejeesh kutty fabbe4981e Update README.md
updated
2016-11-15 16:15:55 -05:00
Rejeesh Kutty 538a1c977f pzsdr2: make files 2016-11-15 16:00:55 -05:00
rejeesh kutty 4905e80df8 Update README.md
updated
2016-11-15 14:16:46 -05:00
Rejeesh Kutty db243df97e pzsdr2- updates 2016-11-15 14:16:06 -05:00
AndreiGrozav 0897716167 fmcadc4: xcvr updates 2016-11-15 16:03:52 +02:00
AndreiGrozav cac4057449 daq2/common: Altera updates 2016-11-15 16:03:52 +02:00
Rejeesh Kutty cfd3ea61f1 pzsdr-to-pzsdr2 2016-11-14 14:12:22 -05:00
Rejeesh Kutty f64b44c8ac sdrstk2pluto- contents 2016-11-11 13:52:57 -05:00
Rejeesh Kutty 2ececad58c sdrstk-2-pluto 2016-11-11 13:49:04 -05:00
Adrian Costina c80033cb1b util_fir_int: removed s_axis_data_tvalid and updated sdrstk 2016-11-11 17:52:19 +02:00
Rejeesh Kutty e62fe0c086 fmcjesdadc1- a5gt/a5soc- sysclk is different 2016-11-11 10:34:18 -05:00
Istvan Csomortani 7008c641b5 axi_adrv9371/zc706: Constraints update
From source *jesd_rstgen* is a false path for TX and RX_OS too.
2016-11-11 10:35:09 +02:00
Rejeesh Kutty 85eac8c811 fmcjesdadc1/a5*- updates 2016-11-10 16:57:06 -05:00
Rejeesh Kutty 959055bd54 common/a5gt- updates 2016-11-10 16:56:35 -05:00
Rejeesh Kutty 7a2c713a4e fmcjesdadc1/a5* - hdlmake.pl 2016-11-10 11:37:06 -05:00
Rejeesh Kutty c6730ab2d7 fmcjesdadc1/a5gt- updates 2016-11-10 11:36:41 -05:00
Rejeesh Kutty c207589f4b fmcjesdadc1/a5gt - qsys2tcl flow 2016-11-10 11:32:29 -05:00
Rejeesh Kutty 8af0731bb0 a5gt- qsys2tcl flow 2016-11-10 11:30:18 -05:00
Adrian Costina 7a606cbae1 sdrstk: Maximum clock frequency is 61.44 in CMOS mode 2016-11-10 17:45:35 +02:00
Adrian Costina d29ef14f36 sdrstk: Configured ad9361 in 1r1t mode 2016-11-10 17:06:42 +02:00
Istvan Csomortani a54092c9bb fmcjesdadc1: Update projects to xcvr framework
This commit contains modifications for Xilinx only
2016-11-10 10:59:52 +02:00
Istvan Csomortani d6918de19e ad6676: Update projects to xcvr frame work 2016-11-10 10:39:46 +02:00
Rejeesh Kutty 3cc416ca60 pzsdr1- fix typo on system_ps7 2016-11-09 12:04:30 -05:00
Istvan Csomortani 35c2dd5d6d adrv9371x/zc706: Fix constraints 2016-11-09 16:34:08 +02:00
Rejeesh Kutty 0b58a2a1db avl_adxcvr- sysclk frequency 2016-11-09 09:21:07 -05:00
Rejeesh Kutty aef3e87d7e fmcjesdadc1/a5soc -- xcvr frame work updates 2016-11-08 15:20:48 -05:00
Rejeesh Kutty 53c2f0642b fmcjesdadc1/a5soc -- xcvr frame work updates 2016-11-08 15:20:33 -05:00
Rejeesh Kutty f0af8216ce common/a5soc- device can not run at 100M cpu clock 2016-11-08 15:19:23 -05:00
Rejeesh Kutty d9cfccc05f common/a5soc- gpio in/out separation 2016-11-08 15:19:02 -05:00
Rejeesh Kutty acb9bf3902 hdlmake- a5soc/a5gt- updates 2016-11-04 15:02:57 -04:00
Rejeesh Kutty 6b492b79db a10soc - remove default assignments 2016-11-04 15:01:19 -04:00
Rejeesh Kutty 8ea9beffaf fmcjesdadc1- a5soc tcl updates 2016-11-04 15:01:19 -04:00
Rejeesh Kutty 4e99c3be9a a5soc- tcl flow updates 2016-11-04 15:01:19 -04:00
Adrian Costina ce3b6a2d3f adrv9371x: Updated constraints for altera projects 2016-11-04 18:20:46 +02:00
Rejeesh Kutty 0dfbb0af11 arradio/c5soc- constraints changes- interface 1r1t 2016-11-03 11:25:52 -04:00
Rejeesh Kutty 128ca7719a ccpci_lvds- rev.d. xcvr pin changes 2016-11-02 16:41:04 -04:00
Rejeesh Kutty 1cbea90bac altera - a10gx bank swap 2016-11-01 12:41:25 -04:00
Rejeesh Kutty 1e0fed82f7 alt_serdes- a10 ddio fixes 2016-11-01 12:41:25 -04:00
Rejeesh Kutty 671a547c2b hdlmake- updates 2016-11-01 12:41:25 -04:00
Adrian Costina d010f3e687 sdrstk: Update Makefile to remove pack/cpack dependancy and add util_fir_dec/util_fir_int dependancy 2016-10-28 16:13:52 +03:00
Adrian Costina ac8a6124af sdrstk: Added interpolation and decimation filters. Removed cpack/upack 2016-10-27 19:33:28 +03:00
Rejeesh Kutty 50552ce7d6 adrv9371x- altera updates 2016-10-27 09:25:00 -04:00
Rejeesh Kutty f752f0c9d7 a10soc- xcvr updates 2016-10-27 09:25:00 -04:00
Adrian Costina d4c7b7ca57 ccusb_lvds: Fixed IIC constraints 2016-10-26 11:12:02 +03:00
Adrian Costina 6607aa707d pzsdr1: Renamed projects to have lvds/cmos sufix 2016-10-26 11:09:43 +03:00
Adrian Costina 9ff92fdf5b pzsdr: Renamed projects to have lvds/cmos sufix 2016-10-26 11:07:29 +03:00
AndreiGrozav b8363d778d arradio: Makefile update 2016-10-25 20:36:56 +03:00
Adrian Costina 138eeebc9b ccusb_lvds: Initial commit 2016-10-25 16:32:44 +03:00
Rejeesh Kutty 5731ba3300 fmcomms11- xcvr updates 2016-10-24 09:51:40 -04:00
Istvan Csomortani 7e57a89ce5 daq1: Add support for A10GX 2016-10-24 11:43:33 +03:00
Rejeesh Kutty c9ac870086 usrpe31x- updates 2016-10-21 13:59:43 -04:00
Rejeesh Kutty 7b958fed87 hdlmake- updates 2016-10-21 13:59:43 -04:00
Rejeesh Kutty 48e90f0e9b usrpe31x- added 2016-10-21 13:59:43 -04:00
Istvan Csomortani 801f980aeb adrv9371: Fix parameter name 2016-10-21 12:50:20 +03:00
Istvan Csomortani 3abd87631a fmcomms11: Fix parameter name 2016-10-21 12:49:48 +03:00
Rejeesh Kutty 7db0c03a92 pzsdr1+ccbox -- updates 2016-10-19 10:32:28 -04:00
Adrian Costina c1b7c5e77a usb_fx3: Added FIFO on the FX3 to Zynq path, between FX3 core and DMA core 2016-10-19 09:30:51 +03:00
AndreiGrozav 17cfdd6be9 fmcomms2/a10gx: Update Makefile and qsys script 2016-10-18 12:42:14 +03:00
Rejeesh Kutty 918ce45e2a pzsdr1/ccbox- updates 2016-10-17 16:29:57 -04:00
Rejeesh Kutty cb97bc500a hdlmake updates 2016-10-17 16:29:57 -04:00
Rejeesh Kutty 950acaed15 ccbox- copy 2016-10-17 16:29:57 -04:00
Adrian Costina 7c541c704a usdrx1: ZC706, Update project to the new GT framework 2016-10-14 18:08:08 +03:00
Adrian Costina 1d1fe26624 fmcomms7: ZC706, Update project to new GT framework 2016-10-14 17:32:23 +03:00
Rejeesh Kutty 5bb77109ca daq2/a10gx- make fix 2016-10-10 13:03:44 -04:00
Rejeesh Kutty 905e29eb01 hdlmake- altera 2016-10-10 12:55:55 -04:00
Rejeesh Kutty e5cf417576 daq2/mb- xcvr procedures 2016-10-10 12:51:30 -04:00
Rejeesh Kutty 273073a584 daq2/kcu105- xcvr procedure 2016-10-10 11:12:47 -04:00
Adrian Costina b3d3876dc5 imageon: ZC706, updated system_top to remove part of the Warnings.
- constraints fixed so Vivado doesn't issue a Warning
2016-10-10 17:33:42 +03:00
Adrian Costina 9efc45f0b6 imageon: Zed, updated system_top to remove part of the Warnings.
- spi csn signals should be tied to 1 if spi is not used
- constraints fixed so Vivado doesn't issue a Warning
2016-10-10 17:31:25 +03:00
Adrian Costina 8875c5bef3 fmcomms6: ZC706, updated system_top to remove part of the Warnings 2016-10-10 16:43:23 +03:00
Istvan Csomortani fcd56a2f90 daq3/a10gx: Update project to the new GT framework
- Update common script
- Update system_top, some port names were changed
- Update constraint files
2016-10-10 16:22:08 +03:00
Adrian Costina 94f55f20e9 adv7511: KCU105, updated system_top to remove part of the Warnings 2016-10-10 16:12:17 +03:00
Adrian Costina f464497062 cn0363: Microzed, updated system_top to remove part of the Warnings 2016-10-10 16:08:59 +03:00
Adrian Costina 2e605fc060 cn0363: Zed, update system_top to remove part of the Warnings 2016-10-10 15:56:46 +03:00
Adrian Costina a12d34a98b adv7511: Zed, updated system_top to remove part of the Warnings 2016-10-10 15:54:34 +03:00
Adrian Costina c737afebf8 adv7511: KC705, updated system_top to remove part of the Warnings 2016-10-10 13:24:40 +03:00
Adrian Costina 74faac9210 ad9467_fmc: KC705, updated system_top to remove part of the Warnings 2016-10-10 13:19:55 +03:00
Rejeesh Kutty ffaf78665f daq2- xcvr procedures 2016-10-06 14:44:20 -04:00
Rejeesh Kutty 3b55822db3 daq2- xcvr connect 2016-10-06 14:09:27 -04:00
Rejeesh Kutty 721ee98a06 zcu102- misc fixes 2016-10-06 10:18:14 -04:00
Istvan Csomortani 8965bcffb7 make: Update make files for DAQ3 2016-10-06 10:27:00 +03:00
Istvan Csomortani 9ace02a227 daq3/a10gx: Update project to the new GT framework 2016-10-06 10:25:25 +03:00
Istvan Csomortani 58c4abd8af daq3/kcu105: Update project to the new GT framework 2016-10-06 10:23:52 +03:00
Rejeesh Kutty ca4dca87e2 daq2- updates 2016-10-05 14:02:59 -04:00
Rejeesh Kutty baabe20766 common/zcu102- spi connections & clock 2016-10-05 14:01:59 -04:00
Istvan Csomortani bab9b2df0b daq3/zc706: Update project with the new transceiver modules 2016-10-05 17:41:25 +03:00
Adrian Costina c196b5bf68 ad6676evb: VC707, fixed system top gpio_bd datawidth 2016-10-05 15:50:43 +03:00
Rejeesh Kutty 0208335ef3 hdlmake- updates 2016-09-30 13:20:22 -04:00
Rejeesh Kutty 27c9bdddb6 daq2/zcu102- 2016.2 updates 2016-09-30 11:55:10 -04:00
Rejeesh Kutty 8e1034946f fmcomms2/zcu102- 2016.2 updates 2016-09-30 11:55:10 -04:00
Rejeesh Kutty 9afff7ae60 common/zcu102- 2016.2 updates 2016-09-30 11:55:10 -04:00
Rejeesh Kutty 33f9ed33c7 projects- ultrascale+ 2016-09-30 11:55:10 -04:00
Rejeesh Kutty 0ded52d8f6 daq2/zcu102- kcu105 copy 2016-09-30 11:55:10 -04:00
Rejeesh Kutty 7290bcc81a hdlmake- updates 2016-09-29 11:50:58 -04:00
Rejeesh Kutty 4950c6c773 adrv9371x - xcvr updates 2016-09-29 11:50:58 -04:00
Rejeesh Kutty 4a5b7fc723 scripts- reconnect added 2016-09-29 11:50:58 -04:00
Adrian Costina e40311eee9 adrv9371x: A10soc, connected DMAs through 128 bit SDRAM0 port at 175MHz 2016-09-29 09:14:37 +01:00
Rejeesh Kutty 4239f64125 dacfifo- board pin warnings 2016-09-27 14:49:20 -04:00
Rejeesh Kutty 751a66eb72 plddr3/zc706- board pin warning 2016-09-26 15:20:37 -04:00
Rejeesh Kutty 79b9e21be8 board- xcvr procedure 2016-09-26 15:20:18 -04:00
Rejeesh Kutty 8314efd4e9 fmcomms11- xcvr updates 2016-09-26 15:19:29 -04:00
Rejeesh Kutty 7fd9280cbf fmcomms11- xcvr updates 2016-09-26 15:19:05 -04:00
Adrian Costina f5809b8817 adrv9371x: a10soc, added adcfifos; connected the new reset to all peripherals; used the new f2sdram1 port 2016-09-24 10:09:05 +03:00
Adrian Costina 2d307d5f58 a10soc: Added system reset bridge. Using F2SDRAM port used in the previous Qsys design 2016-09-24 10:06:35 +03:00
Rejeesh Kutty df37a23a48 pzsdr/ccfmc- rgmii critical warnings fix 2016-09-22 11:38:43 -04:00
Rejeesh Kutty dc6f7bbc4e pzsdr/ccfmc - loopback updates 2016-09-22 11:18:13 -04:00
Rejeesh Kutty 0e2572bbd8 pzsdr- ccbrk_cmos- loopback changes 2016-09-21 13:16:04 -04:00
Rejeesh Kutty 14ad1ea741 pzsdr- swap clear-up 2016-09-21 13:15:40 -04:00
Rejeesh Kutty 21b5e9c634 hdlmake- updates 2016-09-21 11:56:03 -04:00
Adrian Costina 143423e3b9 adrv9371x: A10SOC, fix Makefile and system scripts to be compatible with altera 2016-09-21 18:13:02 +03:00
Adrian Costina 500d8bfb90 adrv9371x: A10GX, fix makefile and system_qsys.tcl script 2016-09-21 18:11:35 +03:00
Rejeesh Kutty 79f34c9de7 ccbrk- test updates 2016-09-21 11:04:22 -04:00
Rejeesh Kutty a2e60cf693 ccbrk - test 2016-09-21 11:04:22 -04:00
Rejeesh Kutty 3ca9fe0919 sdrstk- remove critical warnings from ps7 2016-09-16 14:06:12 -04:00
Istvan Csomortani f1e787f86b fmcomms2: TDD control is enabled by default 2016-09-16 14:45:39 +03:00
Rejeesh Kutty 2a7bc31c01 pzsdr1- disable gpreg constraints 2016-09-15 13:49:04 -04:00
Rejeesh Kutty 67d4e71ff0 pzsdr1- disable gpreg constraints 2016-09-15 12:41:40 -04:00
Istvan Csomortani 16ee1336c3 Makefile: Update make files 2016-09-15 11:41:06 +03:00
Adrian Costina 631923e9f0 usb_fx3: Update to Vivado 2016.2 2016-09-14 15:41:27 +03:00
Istvan Csomortani 9118ca3986 version_upgrade: Update MOTCON2 to 2016.2 2016-09-14 10:58:06 +03:00
Rejeesh Kutty cf9ac730a8 pzsdr1- new rev. board delays 2016-09-13 10:32:13 -04:00
Istvan Csomortani 9a2d2e8a02 version_upgrade: Update FMCADC4 to 2016.2 2016-09-13 15:04:11 +03:00
Rejeesh Kutty 236a938425 daq2/a10gx- qsys updates 2016-09-12 14:57:50 -04:00
Rejeesh Kutty 5df30ac6b0 daq2/a10gx- xcvr sharing 2016-09-12 14:57:50 -04:00
Adrian Costina 521c41ce32 adrv9371x: Updated a10soc project. Common design differentiates between nios and a10soc carrier 2016-09-08 11:44:45 +03:00
Adrian Costina 40c9fc92c1 a10soc: Switched to tcl flow 2016-09-08 11:31:06 +03:00
Adrian Costina 0d095f5da9 a10gx: Added system_type variable in common design 2016-09-08 11:29:14 +03:00
Istvan Csomortani bae63ae5b1 version_upgrade: Update the DAQ3 project to 2016.2 2016-09-06 11:41:37 +03:00
Istvan Csomortani b8c34791d5 version_upgrade: fmcjesdadc1 updated to 2016.2
Xilinx IP core JESD204 is updated to version 7.0
2016-09-06 11:41:37 +03:00
AndreiGrozav b837883b98 pzsdr1/pzsdr1/pzsdr1_cmos_system_constr: Fixed voltage level selection 2016-09-01 17:16:59 +03:00
AndreiGrozav 93fa5aeec3 fmcadc2/vc707: Add adf4355 access, update design to Vivado 2016.2 2016-09-01 16:11:39 +03:00
Adrian Costina dc21384002 pzsdr: Update ccpci base design 2016-09-01 09:06:30 +03:00
Rejeesh Kutty 2f9ac4a342 altera- qsys-script does not support most tcl commands 2016-08-30 11:50:36 -04:00
Rejeesh Kutty 917da79da1 altera- source defaults for qsys-script 2016-08-30 11:50:36 -04:00
Rejeesh Kutty 8192e755e1 altera- defaults 2016-08-30 11:50:36 -04:00
AndreiGrozav 1eccf5af07 fmcomms7: Update common design to Vivado 2016.2 2016-08-30 16:46:15 +03:00
AndreiGrozav 2015bcedaa fmcadc2: Update common design to Vivado 2016.2 2016-08-30 16:42:58 +03:00
Adrian Costina 6f0d124861 fmcadc5: Update to Vivado 2016.2 2016-08-30 16:09:28 +03:00
Adrian Costina 4248b9373a ad6676evb: Update to Vivado 2016.2 2016-08-30 16:08:07 +03:00
AndreiGrozav a6e6b3f96e version_upgrade: Update fmcomms1 common design to Vivado 2016.2 2016-08-29 15:59:15 +03:00
AndreiGrozav 2e59f377e1 version_upgrade: Update ac701, mitx045 and zed common design to Vivado 2016.2 2016-08-29 09:50:46 +03:00
Rejeesh Kutty 271029768c pzsdr/cmos - swap==1 2016-08-26 10:31:00 -04:00
Adrian Costina d18f6aa816 adrv9371x: A10GX, added adcfifo
- connected dac dma to 133 MHz clock
- set explicit clock rate to xcvr reference clock bridge
2016-08-26 14:46:48 +03:00
Istvan Csomortani 5cc2ab37a5 version_upgrade: Common ZC702 get an upgrade to 2016.2
Xilinx IP Clock Wizard updated to version 5.3
2016-08-26 10:20:04 +03:00
Istvan Csomortani cd0c981b50 projects/scripts: Fix to prevent a warning
In case of axi_interconnects, when just one slave and master interface is
active, the 'Interconnect Optimization Strategy' is disabled. So this
parameter should be set just if there is more than one slave interface.
2016-08-26 10:08:00 +03:00
Istvan Csomortani 6ab137a0e9 projects/scripts: Cosmetics 2016-08-26 10:07:08 +03:00
Istvan Csomortani 9dfcfe6146 version_upgrade: adv7511 common script to 2016.2
Xilinx IP Clock Wizard updated to version 5.3
2016-08-26 09:52:01 +03:00
Rejeesh Kutty 264bde77ad sdrstk- SWAP==1 option 2016-08-24 12:07:13 -04:00
Adrian Costina 3c6cfdc7b5 adrv9371x: A10GX, switched TX lanes 2016-08-24 18:06:14 +03:00
Adrian Costina 215edb11c6 adrv9371: A10GX, updated design
- disable reconfiguration for RX transceivers and enabled the reconfiguration for TX transceiver. They cannot be enabled at the same time at this point
- update FIFO SIZE to 16 for all DMAs
- updated memory connections to 256 bit and moved clock connection to 133 MHz, for all DMAs.
2016-08-23 18:25:48 +03:00
Rejeesh Kutty 320f87d63b sdrstk- fix spi/port connections 2016-08-22 16:52:43 -04:00
Adrian Costina 270f8a6bbe adrv9371x: Updated project common 2016-08-22 16:58:21 +03:00
Adrian Costina f1b834ab25 scripts: Update script so that all interconnects are optimized for performance 2016-08-22 16:56:02 +03:00
Adrian Costina c6b065c349 zc706: Updated DDR3 dacfifo 2016-08-22 16:48:52 +03:00
Rejeesh Kutty f697490de6 hdlmake- updates 2016-08-19 15:59:41 -04:00
Rejeesh Kutty 5c35012f54 sdrstk- updates 2016-08-19 15:59:13 -04:00
Rejeesh Kutty 8582517712 sdrstk- updates 2016-08-19 15:56:48 -04:00
Rejeesh Kutty 67bf8f8e78 scripts- fix path and device defaults and override 2016-08-19 15:56:07 -04:00
Rejeesh Kutty 6ef9555909 sdrstk- added 2016-08-19 13:45:40 -04:00
Adrian Costina 41203d07e9 adrv9371x: A10GX, update SPI connection 2016-08-18 17:42:27 +03:00
dbogdan 03c83b59bf adrv9371x/a10soc: Export axi_ad9371_s and xcvr_reconfig_avmm 2016-08-17 19:03:53 +03:00
Rejeesh Kutty 5d0e08d92e common/vc707- 2016.2 version 2016-08-17 10:36:19 -04:00
Rejeesh Kutty 73413366bc daq2/all - warnings fix 2016-08-17 10:36:00 -04:00
Rejeesh Kutty 0b6fbf2208 daq2/vc707- 2016.2 updates 2016-08-17 10:34:06 -04:00
Rejeesh Kutty ce1fed1ce6 dmafifo- adc/dac split 2016-08-16 12:54:39 -04:00
Rejeesh Kutty 0694a5015d kc705- 2016.2 version 2016-08-16 12:54:39 -04:00
Rejeesh Kutty 8311098384 daq2/kc705- adxcvr changes 2016-08-16 12:54:39 -04:00
Rejeesh Kutty 8464816c82 dmafifo-split to adc/dac 2016-08-16 12:54:39 -04:00
Adrian Costina eb55f600fb adrv9371x: Initial commit
-need to fix dc filter module for AD9371 / altera
2016-08-16 15:50:46 +03:00
Adrian Costina 5c27ccd1fa adrv9371x: Added common qsys tcl 2016-08-16 15:34:10 +03:00
dbogdan 4658686ae1 adrv9371x/a10soc: Misc changes for being able to run Linux 2016-08-16 11:56:25 +03:00
Dragos Bogdan 39c1c83d00 adrv9371x/a10soc: Fix spi_csn assignment 2016-08-12 10:07:11 +03:00
Adrian Costina 0b0aa8e6c0 Makefile: Add MMU option to altera makefiles 2016-08-11 17:46:54 +03:00
Rejeesh Kutty 5d93e542ed daq2-kcu105: 2016.2 updates 2016-08-11 10:00:41 -04:00
Rejeesh Kutty 16ad0f4379 kcu105- 2016.2 update 2016-08-11 10:00:41 -04:00
Adrian Costina 285059aed0 kcu105: Don't use phy reset automation, as it's not supported for KCU105 2016-08-09 10:19:57 +03:00
Adrian Costina 452d4706d3 kcu105: Update base project to 2015.4.2
- change part to revision 1.1 of the board
2016-08-09 10:19:36 +03:00
Rejeesh Kutty c6f4def93d altera- make mmu a make switch 2016-08-08 11:54:51 -04:00
Istvan Csomortani 0cd608a7e2 lib_refactoring: Update Make files 2016-08-08 16:38:38 +03:00
Istvan Csomortani df36902713 lib_refactoring: Fix path of the IO macros 2016-08-08 15:07:19 +03:00
Istvan Csomortani f784557895 lib_refactoring: IOBUF is a Xilinx macro, no need to use with Altera 2016-08-08 15:06:34 +03:00
Lars-Peter Clausen 8f61e11a70 pzsdr: ccpci: Add PCIe reset monitor
For reliable and correct operation it is vital that the FPGA is fully
configured and up and running before the PCIe host de-asserts the reset.

Add a small logic circuit that detects de-assertion of the reset signal
that can be used to verify that the reset de-assertion was seen by the
FPGA.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2016-08-05 18:31:40 +02:00
Lars-Peter Clausen 91782989ad pzsdr: ccpci: Set IO standard to LVCMOS33 for banks 12 and 13
The IO voltage for bank 12 and 13 is 3.3V on the PCIe carrier. Set the
IOSTANDARD of the pins on these banks accordingly.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2016-08-05 18:31:40 +02:00
Lars-Peter Clausen 418217dd10 pzsdr: Remove LED and button signals from PCIe carrier
Only the FMC carrier and the breakout board do have push buttons and LEDs.
They are not present on the PCIe carrier. So move the constraints to a
separate file that can be included by the projects that need them and
remove all LED and button related signals from the PCIe project.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2016-08-05 18:31:40 +02:00
Lars-Peter Clausen 3cff0fa7dc pzsdr: ccpci: Use PL SPI and GPIO peripherals
To be able to access the GPIO pins and the SPI port through the PCIe bridge
we need to use the PL SPI and GPIO controllers rather than the PS
controllers. Adjust the sytem_top.v accordingly so that the PL peripherals
are connected to the external pins.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2016-08-05 18:29:42 +02:00
Adrian Costina d60bce654c Makefiles: Updated Makefiles so they run correctly with gnuwin32 tools 2016-08-05 15:16:04 +03:00
Rejeesh Kutty e42b4ea378 hdlmake- updates 2016-08-04 13:28:25 -04:00
Rejeesh Kutty ed9e92621c daq2- spi+xcvr address conflict 2016-08-04 10:50:31 -04:00
Adrian Costina 999eccc134 daq3: Update A10GX project to Quartus 16.0 2016-08-01 16:19:43 +03:00
Adrian Costina 9a563de8ff daq2: A10GX updated project to Quartus 16.0
- connected directly axi_ad9680 to xcvr_core, skipping axi_jesd_xcvr
2016-08-01 15:09:53 +03:00
Adrian Costina 52ae3ddd6c a10gx: Updated common files to 16.0 2016-08-01 15:08:12 +03:00
Istvan Csomortani 7ca8e10004 make: Update Make files 2016-08-01 14:24:48 +03:00
Istvan Csomortani af4c43b6e1 hdl-vivado-2016.2: Update fmcomms2 and pzsdr base design 2016-08-01 13:49:12 +03:00
Istvan Csomortani fbe3d75eb0 cosmetics: Delete trailing whitespace characters 2016-08-01 13:46:46 +03:00
Shrutika Redkar 9952a94efb hdl-vivado-2016.2- ip version updates 2016-07-28 13:44:57 -04:00
Shrutika Redkar 6ffe59728b hdl-vivado-2016.2- update 2016-07-28 13:44:57 -04:00
Shrutika Redkar 3b2bde2fa1 hdl-vivado-2016.2- min. addr-space requirement 2016-07-28 13:44:57 -04:00
Adrian Costina 08f4ba24d5 usb_fx3: Switch PS7 UART to UARTLITE to communicate with the FX3 board 2016-07-28 15:21:38 +03:00
Rejeesh Kutty 39a5534e00 hdlmake- updates 2016-07-21 16:10:38 -04:00
Rejeesh Kutty 6df5ba1a7a daq2- adxcvr version 2016-07-21 16:09:33 -04:00
Rejeesh Kutty 4532e5c0cb fmcomms11- support iq mode 2016-07-21 11:58:03 -04:00
Rejeesh Kutty c75289be21 fmcomms11- use qpll tx-12g5, cpll rx-6g25 2016-07-19 16:21:49 -04:00
Shrutika Redkar d6243f3d01 update in fmcomms11 tcl and clock constrains 2016-07-18 09:04:13 -04:00
Lars-Peter Clausen 44d9f98e12 adi_project.pl: Fix ADI_NO_BITSTREAM_COMPRESSION detection logic
Only enable bitstream compression only if both the
ADI_NO_BITSTREAM_COMPRESSION environment and TCL variable are not set.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2016-07-14 10:44:42 +02:00
Lars-Peter Clausen 62c7114d77 Enable bitstream compression for Xilinx projects
Enabling bitstream compression reduces the size of the generated bitstream.

This means on one hand it will consume less storage, which is especially
useful for the BOOT partition of the ADI images where we store BOOT.BIN
files for all supported platforms.

On the other hand a smaller bitstream is faster to load from the storage
medium and it is also faster to program to the FPGA. So it reduces the
overall boot time as well.

The only downside of bitstream compression is that the bitstream size is no
longer constant, but depends on the actual design and resource utilization.
This will not work with bootloaders that expect a fixed size.

When building a bitstream using the tcl scripts bitstream compression can
be disabled by setting the ADI_NO_BITSTREAM_COMPRESSION environment
variable.

Initial tests show a reduction of a round 50% in size for most ADI
projects.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2016-07-14 10:16:15 +02:00
AndreiGrozav 12abe2b6b9 fmcomms2: Makefile update 2016-07-12 09:39:24 +03:00
AndreiGrozav 283bf9ad75 fmcomms2_a10GX: Add fmcomms2 on a10gx 2016-07-11 18:37:18 +03:00
AndreiGrozav e9fe752b7a fmcomms2_qsys.tcl: Add fmcomms2 block design script for Altera 2016-07-11 18:34:21 +03:00
Adrian Costina 92c580a84d daq3: A10GX, updated project to the TCL flow 2016-07-08 12:00:37 +03:00
Istvan Csomortani 7be017baa3 daq1: Add AXI PLDDR FIFO to the receive path
The AD9684 has two 500 MSPS converter, the system can not handle this
throughput without a FIFO.
2016-07-07 07:15:54 +03:00
Istvan Csomortani 9169e20b5e daq1: Fix the data width on the DMAC interfaces
+ HP ports maximum width is 64 bits
+ DMAC's default width is 64, no need for redefinition
2016-07-07 07:15:54 +03:00
Rejeesh Kutty 48762519b5 make updates 2016-07-06 15:02:00 -04:00
Istvan Csomortani 427cc84bb2 axi_ad7616: Rename the physical interface signals to rx_*
No functional modification.
2016-07-01 14:45:23 +03:00
AndreiGrozav 69a68a99e0 imageon/zed - remove onboard hdmi and update design 2016-07-01 14:11:49 +03:00
Shrutika Redkar ad491ec04a updated tcl files after inclusion of ad9162 core 2016-06-30 13:26:16 -04:00
Adrian Costina c6c3622816 a10gx: Updated common design adding explicit clock frequency and synchronous reset deassertion 2016-06-30 10:59:29 +03:00
Istvan Csomortani 8d558b2538 make: Update Make files 2016-06-29 14:50:07 +03:00
Istvan Csomortani e6494b9a74 axi_ad7616: Change the DMA interface type to Write FIFO 2016-06-29 14:11:02 +03:00
Istvan Csomortani 64633e519c Merge remote-tracking branch 'origin/dev_ad7616' into dev 2016-06-29 12:32:39 +03:00
Istvan Csomortani 2e80dec513 adrv9371x/zc706: Update project with the new axi_dacfifo 2016-06-22 12:33:47 +03:00
Rejeesh Kutty 67c948e821 fmcomms2/a10soc-- bad board design 2016-06-14 12:29:36 -04:00
Rejeesh Kutty 8f48a5520a makefile updates 2016-06-10 14:26:46 -04:00
Rejeesh Kutty eaf4d4a19d makefile updates 2016-06-10 14:26:14 -04:00
Rejeesh Kutty 1746701d45 fmcomms11- updates 2016-06-10 14:20:43 -04:00
Rejeesh Kutty 509f031d58 fmcomms11- updates 2016-06-10 14:20:43 -04:00
Rejeesh Kutty fdc1240cc8 fmcomms11- spi 2016-06-10 14:20:43 -04:00
Rejeesh Kutty 8f00760c13 fmcomms11- initial commit 2016-06-10 14:20:43 -04:00
Istvan Csomortani f84fafaaac adrv9371x/zc706: Fix system top
The dac_fifo_bypass gpio is an internal gpio only. No need for IOBUF.
2016-06-10 10:11:27 +03:00
Rejeesh Kutty 468800bb38 daq2/a10gx- makefile update 2016-06-07 14:06:42 -04:00
Rejeesh Kutty 625052f46e daq2/a10gx- qsys updates 2016-06-07 12:28:04 -04:00
Rejeesh Kutty d53b06849e daq2/a10gx- qsys updates 2016-06-07 12:28:04 -04:00
Rejeesh Kutty ae1dd1d58e daq2/a10gx- qsys updates 2016-06-07 12:28:04 -04:00
Rejeesh Kutty 3516ec28b7 daq2/a10gx- qsys updates 2016-06-07 12:28:04 -04:00
Rejeesh Kutty 3351ff607e adrv9371x- need to investigate merge with avalon 2016-06-02 16:22:53 -04:00
Rejeesh Kutty ebdc7832a7 hdl make updates 2016-06-01 14:00:30 -04:00
Rejeesh Kutty bfeebc2791 imageon/zc706- remove onboard hdmi 2016-06-01 13:59:13 -04:00
Rejeesh Kutty eca4d4e2a6 imageon/zc706- board updates 2016-06-01 13:59:13 -04:00
Rejeesh Kutty c293c04634 hdl make updates 2016-06-01 13:53:09 -04:00
Rejeesh Kutty 46b464ed72 adrv9371/a10soc- qsys updates 2016-06-01 13:48:51 -04:00
Rejeesh Kutty a958ef27da adrv9371- qsys updates 2016-06-01 13:48:51 -04:00
Rejeesh Kutty 5b2a90ffff adrv9371- qsys 2016-06-01 13:48:51 -04:00
Rejeesh Kutty af45acfcb9 ad9371- qsys updates 2016-06-01 13:48:51 -04:00
Rejeesh Kutty d2fc64d130 daq3/a10gx: updates 2016-05-27 08:37:47 -04:00
AndreiGrozav d10dd78094 kcu105: Update common design to 2015.4 2016-05-27 14:59:28 +03:00
Istvan Csomortani 1853c6921d adrv9371x/zc706: Fix typo in system_top 2016-05-27 14:13:55 +03:00
Istvan Csomortani a6fbf6c20b adrv9371x: Update the Makefiles 2016-05-27 14:13:55 +03:00
Istvan Csomortani 32d46389f2 adrv9371x: Move GTs AXI interface to HP3
If the VDMA and the GTs AXI are connected to the same HP port, the
HDMI won't work on full resolution (1080p). Care should be taken, this can
affect the receive and observation paths (both are connected to HP2).
2016-05-27 14:13:55 +03:00
Istvan Csomortani b452a8e2d4 adrv9371x: Connect bypass and data underflow 2016-05-27 14:13:55 +03:00
Istvan Csomortani 3859cba186 adrv9371x/zc706: Add PL_DDR FIFO to the design 2016-05-27 14:13:55 +03:00
Istvan Csomortani d0b40afb45 zc706/common: Fix PL_DDR3 fifo integration script 2016-05-27 14:13:55 +03:00
Istvan Csomortani aca3038919 axi_dacfifo: No overflow for DAC 2016-05-27 14:13:55 +03:00
Istvan Csomortani 81ade7f26c axi_dacfifo: Fix resets
DMA side: axi_resetn is used to reset the address counters
DAC side: GT tx_rst is used to reset the last_address register
2016-05-27 14:13:55 +03:00
Istvan Csomortani 578376c8fe axi_dacfifo: Add bypass logic 2016-05-27 14:13:55 +03:00
Rejeesh Kutty 9c6e80fca2 daq3/a10gx- qsys modifications 2016-05-24 03:15:45 -04:00
Rejeesh Kutty 39d23032f1 daq2- qsys updates 2016-05-23 10:55:44 -04:00
Rejeesh Kutty 0d1c4d232e a10soc- updates-1 2016-05-20 16:14:57 -04:00
Rejeesh Kutty 09520709b0 make updates 2016-05-20 12:35:45 -04:00
Rejeesh Kutty f92e8509bb adrv9371x- added 2016-05-20 11:46:25 -04:00
Rejeesh Kutty 50d018fc11 arradio- rfifo/wfifo added 2016-05-18 13:24:13 -04:00
Rejeesh Kutty e345953bdd arradio- updates 2016-05-16 12:19:38 -04:00
Adrian Costina 72151bb1a6 a10gx: Updated base design to include MMU 2016-05-13 18:44:41 +03:00
Rejeesh Kutty f3f5353944 zcu102- updates 2016-05-10 15:40:41 -04:00
Rejeesh Kutty 16e3a0e569 zcu102- updates 2016-05-10 15:40:41 -04:00
Rejeesh Kutty e1350018da zcu102- updates 2016-05-10 15:40:41 -04:00
Rejeesh Kutty a6411dbd63 zcu102- added 2016-05-10 15:40:41 -04:00
Rejeesh Kutty e8fbdd0f5d zcu102: zynq ultrascale 2016-05-10 15:40:41 -04:00
Rejeesh Kutty 0041bf69be c5soc- remove unused hps ports 2016-05-09 13:54:08 -04:00
Rejeesh Kutty 89b20f2a35 c5soc- remove unused hps ports 2016-05-09 13:54:08 -04:00
AndreiGrozav 8d72b645ae fmcomms2/common: Remove ila_tdd block 2016-05-09 10:28:10 +03:00
Istvan Csomortani b0538a03a2 Make: Update 2016-05-06 16:44:24 +03:00
Istvan Csomortani 4863a04132 axi_adc/dacfifo: Split the intergration script file
Split the integration script file into two separate script files. Rename the
integration processes names to be more meaningful.
2016-05-05 09:53:55 +03:00
Rejeesh Kutty ddfaff2cf5 fmcomms2/a10soc: compile version 2016-05-04 13:42:12 -04:00
Rejeesh Kutty f4e5965936 fmcomms2/a10soc: ip updates 2016-05-04 13:42:12 -04:00
Rejeesh Kutty 92dcce1674 a10soc: default ports 2016-05-04 13:42:12 -04:00
AndreiGrozav be74db656c ad6674evb, fmcadc2, fmcadc4, fmcadc5, fmcjesdadc1:
Update system_project.tcl scripts to correctly select the necessary
constraint files
2016-05-04 19:37:33 +03:00
AndreiGrozav 3ca3414522 fmcadc2: Fixed bus data width 2016-05-04 19:20:01 +03:00
AndreiGrozav 9104b2cc60 ad6676evb, fmcadc2, fmcadc4, fmcadc5,...
ad6676evb, fmcadc2, fmcadc4, fmcadc5, fmcjesdadc1: Remove unused
set_proprieties
2016-05-04 19:13:25 +03:00
Rejeesh Kutty 385ed31a45 make files update 2016-04-29 10:17:35 -04:00
Rejeesh Kutty 61b531b1c1 a10soc device update 2016-04-29 10:17:35 -04:00
Istvan Csomortani 160d54f311 ad7616_sdz: Some comment rephrase 2016-04-29 16:41:35 +03:00
Rejeesh Kutty 664ea16a0f ccpci- carrier changes 2016-04-27 16:26:11 -04:00
Rejeesh Kutty e790e4c3ae a10soc- complete qsys 2016-04-25 12:56:19 -04:00
Rejeesh Kutty bfa6fe2a40 a10soc- updates 2016-04-25 11:23:16 -04:00
Rejeesh Kutty 28159aeec9 a10soc- updates 2016-04-25 11:11:46 -04:00
Rejeesh Kutty 0a3967b886 a10soc- updates 2016-04-25 10:53:26 -04:00
Rejeesh Kutty d36d1263c5 a10soc- updates 2016-04-25 10:50:09 -04:00
Istvan Csomortani 1fd5c0f28b ad7616_sdz: Fix IO definitions for the parallel interface. 2016-04-25 10:56:45 +03:00
Istvan Csomortani 6de356e8fc ad7616_sdz: Fix the data width at i_iobuf_adc_cntrl 2016-04-25 10:55:37 +03:00
Rejeesh Kutty 2a5f31d26b fmcomms2/a10soc- copy 2016-04-22 15:15:44 -04:00
Rejeesh Kutty 82c4f75f13 a10soc- a10gx copy 2016-04-22 10:39:21 -04:00
Rejeesh Kutty 7a4a7edfba daq2/a10gx: 10AX115S3F45E2SGE3 version 2016-04-20 16:07:41 -04:00
Rejeesh Kutty e00236e5fd daq2/a10gx: 10AX115S3F45E2SGE3 version 2016-04-20 16:04:46 -04:00
Rejeesh Kutty 8b2542b181 daq2/a10gx: 10AX115S3F45E2SGE3 version 2016-04-20 16:01:12 -04:00
AndreiGrozav 679d471d75 Merge branch 'hdl_2016_r1' into dev
hdl_2016_r1 contains IP core upgrades to Vivado 2015.4.2 and hdmi_tx improvements.
2016-04-19 18:05:50 +03:00
Adrian Costina 402253d308 usb_fx3: Updated design to include the GPIF II interface 2016-04-19 15:52:30 +03:00
Istvan Csomortani 8a574cd8ba zc706_system_plddr3.tcl : Add integration process for the AXI_DAC_FIFO 2016-04-19 11:30:52 +03:00
AndreiGrozav c291f8f107 daq1: Updated design to 2015.4 2016-04-14 23:36:47 +03:00
AndreiGrozav 469b4ea5e8 fmcadc5: Updated design to 2015.4 2016-04-14 23:18:23 +03:00
AndreiGrozav 62bd057106 fmcadc5/common: Update common design to 2015.4 2016-04-14 23:01:38 +03:00
Rejeesh Kutty a88ced8136 pzsdr1: lvds/cmos updates 2016-04-11 16:18:29 -04:00
Rejeesh Kutty 3006c5a223 make updates 2016-04-11 16:14:59 -04:00
Rejeesh Kutty 736bbdd95a pzsdr1- io updates 2016-04-11 16:12:21 -04:00
Rejeesh Kutty 8a5a5082f3 pzsdr1- io updates 2016-04-11 16:12:09 -04:00
Rejeesh Kutty 8e689f4594 pzsdr1- lvds/cmos constraints 2016-04-11 16:00:18 -04:00
Rejeesh Kutty 7e807d83b1 pzsdr1- cmos mode 2016-04-11 15:58:29 -04:00
Rejeesh Kutty bf6ef4e5f3 board- add disconnect 2016-04-11 15:33:00 -04:00
Rejeesh Kutty 68bc647472 pzsdr1- ddr board delays update 2016-04-06 15:30:27 -04:00
AndreiGrozav 21208ca208 Makefiles: Update Makefiles 2016-03-31 12:37:47 +03:00
Istvan Csomortani 1fab6ce477 daq2/common: Add util_dacfifo/dac_xfer_out control 2016-03-29 16:55:33 +03:00
Istvan Csomortani 255b0ebd40 util_dacfifo: Add dac_xfer_out control
The dac_xfer_out control signal is asserted while the DAC reads back data. Should be connected to upack/dma_xfer_in.
2016-03-29 16:50:00 +03:00
Adrian Costina 657144d9a7 a10gx: Updated base design and DAQ2 to the new revision of the a10gx board
- tried using ATX PLL and fPLL for TX transceiver clocks, but could not get them to lock
- CMU PLL works correctly as temporary solution
2016-03-28 13:21:36 +03:00
Istvan Csomortani 7ce3f6e274 ad7616_sdz: Fix system top for parallel interface mode. 2016-03-24 13:49:30 +02:00
Istvan Csomortani a1c2c61884 ad7616_sdz: Update the IOBUF instance names 2016-03-24 11:46:33 +02:00
AndreiGrozav 7c2f34549b motcon2_fmc: Update common design to 2015.4 2016-03-23 10:27:07 +02:00
Istvan Csomortani 373481360b util_dacfifo: Add a bypass option to the FIFO 2016-03-21 14:14:43 +02:00
AndreiGrozav 714caa964c usdrx1: Update common design to 2015.4 2016-03-18 16:29:43 +02:00
AndreiGrozav 05f4f3ac09 usb_fx3: Update common design to 2015.4 2016-03-18 16:16:38 +02:00
AndreiGrozav 24fdd2b9b7 pzsdr/ccpci: Update common design to 2015.4 2016-03-18 15:30:10 +02:00
AndreiGrozav f8b155faab pzsdr/ccfmc: Update common design to 2015.4 2016-03-18 15:28:56 +02:00
AndreiGrozav d567af54ef imageon: Update common design to 2015.4 2016-03-18 15:27:31 +02:00
AndreiGrozav 995debedce fmcomms2: Update common design to 2015.4 2016-03-18 15:26:52 +02:00
AndreiGrozav b555be25d5 kcu105: Update common design to 2015.4 2016-03-18 15:22:42 +02:00
AndreiGrozav 412013d939 adv7511: Update common design to 2015.4 2016-03-18 15:01:25 +02:00
AndreiGrozav d355aa0ea6 daq3/zc706: Updated design to 2015.4 2016-03-17 11:46:48 +02:00
AndreiGrozav 012b095006 daq3: Updated common design to 2015.4 2016-03-17 11:44:27 +02:00
AndreiGrozav 38c3f7474a ad6676: Updated common design to 2015.4 2016-03-17 11:40:46 +02:00
AndreiGrozav abc03fff2c fmcomms7: Updated design to 2015.4 2016-03-17 09:11:41 +02:00
AndreiGrozav 59c726ecbe fmcjesdadc1: Updated common design to 2015.4 2016-03-16 10:14:06 +02:00
AndreiGrozav 1a3aab0c13 fmcomms1: Updated common design to 2015.4 2016-03-16 10:09:54 +02:00
AndreiGrozav b7be089b82 daq2: Updated common design to 2015.4 2016-03-16 10:02:42 +02:00
Rejeesh Kutty 697469ee28 daq1- updates 2016-03-15 12:39:38 -04:00
AndreiGrozav 334fce03a3 fmcadc4/zc706: Updated design to 2015.4 2016-03-15 15:28:11 +02:00
AndreiGrozav e8dd5f9788 fmcadc4: Updated common design to 2015.4 2016-03-15 15:27:25 +02:00
AndreiGrozav 98cc7dad7d fmcadc2: Updated common design to 2015.4 2016-03-15 15:26:05 +02:00
AndreiGrozav ceea7f25b2 fmcomms2: Updated common design to 2015.4 2016-03-15 15:23:20 +02:00
AndreiGrozav 6f03998b95 zc702: Updated common design to 2015.4 2016-03-15 15:21:22 +02:00
AndreiGrozav a0c5f46940 zed: Updated common design to 2015.4 2016-03-15 15:20:46 +02:00
AndreiGrozav 9a258d5e4c vc707: Updated common design to 2015.4 2016-03-15 15:20:02 +02:00
AndreiGrozav bcf5bd8137 mitx045: Updated common design to 2015.4 2016-03-15 15:18:31 +02:00
AndreiGrozav 27f5f1dcbe kc705: Updated common design to 2015.4 2016-03-15 15:17:53 +02:00
AndreiGrozav eb743e0e03 ac701: Updated common design to 2015.4 2016-03-15 15:17:02 +02:00
AndreiGrozav d282064103 zc706: Updated common design to 2015.4 2016-03-15 15:16:36 +02:00
AndreiGrozav 71be9519ec adi_project.tcl: Updated to 2015.4 2016-03-15 15:03:50 +02:00
Adrian Costina 33b265a742 Makefile: Update Makefiles 2016-03-14 09:31:17 +02:00
Rejeesh Kutty 561412e322 pzsdr-cmos swap 2016-03-11 11:25:58 -05:00
Rejeesh Kutty c7ee15d4f4 ccbrk_cmos: cmos mode 2016-03-11 11:25:58 -05:00
Rejeesh Kutty c566784ba9 ccbrk_cmos: ccbrk copy 2016-03-11 11:25:58 -05:00
Istvan Csomortani 573146aa96 axi_ad7616: Fix the data width of the AXI stream interface 2016-03-10 16:38:53 +02:00
Istvan Csomortani b0f90bd0e8 daq1/cpld: Read interface fix 2016-03-04 20:28:24 +02:00
Istvan Csomortani 7e607957ee daq1.cpld: Prevent the spi_counter to roll over. 2016-03-04 20:28:22 +02:00
Istvan Csomortani 262a42c676 daq1/cpld: Update CPLD_VERSION value 2016-03-04 20:28:20 +02:00
Istvan Csomortani 9439862301 daq1/cpld: Update CPLD
Change to control line fpga_to_cpld to cpld_to_fpga, this is not a functional change.
2016-03-04 20:28:18 +02:00
Rejeesh Kutty 3466f21f8e pzsdr add cmos/lvds support 2016-03-04 10:39:48 -05:00
Rejeesh Kutty 18f30c8dc8 pzsdr- cmos/lvds split 2016-03-04 10:39:48 -05:00
Rejeesh Kutty a2374f64bf pzsdr- cmos/lvds split 2016-03-04 10:39:48 -05:00
Adrian Costina 977d9d0624 Merge branch 'hdl_2015_r2' into dev
Conflicts:
	projects/daq1/common/daq1_spi.v
2016-03-02 13:52:15 +02:00
Adrian Costina 40fb68dfd5 ad9265, ad9434, ad9467, daq1, daq2, daq3, fmcadc2, fmcadc4, fmcadc5, fmcjesdadc1, fmcomms6, fmcomms7, usdrx1: updated common spi module so that spi streaming is possible 2016-03-02 13:39:37 +02:00
Adrian Costina becc23a69b daq2: Modified common spi module so that spi streaming is possible
- stop incrementing spi_count after the instruction cycle
2016-03-01 17:25:58 +02:00
Rejeesh Kutty f7e490c2b3 hdlmake.pl updates 2016-02-26 13:46:11 -05:00
Rejeesh Kutty e012d0519b Merge remote-tracking branch 'origin/hdl_2015_r2' into dev 2016-02-26 13:39:39 -05:00
Rejeesh Kutty f6e64e42b0 kcu105: add ethernet idelaycntrl 2016-02-26 13:19:49 -05:00
Istvan Csomortani 59313f3c90 daq1: ADC DMA must be in none-cyclic mode 2016-02-24 14:37:19 +02:00
Istvan Csomortani c0a559a9b1 daq1: Fix some typos in the SPI wrapper 2016-02-24 14:31:56 +02:00
Adrian Costina 8ccd8d87bb daq2: A10GX, increase analog/digital reset durations
- reset the xcvr_rst_cntrl only from the axi_jesd_xcvr
- checked separate RX/TX reset per channel
2016-02-23 11:41:38 +02:00
Adrian Costina 89f7aadfb1 fmcjesdadc1: A5GT, connected xcvr_rxt_cntrl reset input to the axi_jesd_xcvr reset output
This will allow for the transceivers to be reset by the axi_jesd_xcvr core
2016-02-23 11:31:07 +02:00
Rejeesh Kutty 4fb6589b2d pzsdr/ccfmc: add fan controls 2016-02-19 16:40:54 -05:00
Adrian Costina 377461e0d4 Merge branch 'hdl_2015_r2' into dev 2016-02-19 14:15:27 +02:00
Adrian Costina 0f37dd6424 fmcjesdadc1: Fixed project
- changed system_project.tcl so that all base designs to be included
- changed DMA properties to take into consideration the new parameter names
- changed reset bridges to asynchronous
- increased maximum burst size of the DMA bridge
- changed the data_width of the memory bus to 256, as with 512 timing violations may occur
- changed base addresses for the base system to be the same as in the previous release
2016-02-19 14:09:57 +02:00
Rejeesh Kutty ce760eb691 fmcadc2- add adf4355 access 2016-02-18 16:17:33 -05:00
Adrian Costina d94f157454 arradio: Changed ADC/DAC DMA address length to 24 bit 2016-02-16 15:27:51 +02:00
Adrian Costina 43e03ca6f7 arradio: Updated project
- made the reset bridges asynchronous
- connected the arradio gpio to the CPU interconnect
2016-02-16 14:50:23 +02:00
Istvan Csomortani 5518c47ca4 daq1_cpld: Set Input and tristate I/O termination mode to FLOAT 2016-02-15 19:27:59 +02:00
Istvan Csomortani 051ac307e6 daq1_cpld: Do not forward the first eight clock cycles of fmc_spi_sclk to sclk 2016-02-15 19:26:58 +02:00
Istvan Csomortani 9370246cfa daq1: Fix bugs on CPLD design
Fix the CSN forwarding.
2016-02-12 16:59:09 +02:00
Istvan Csomortani 5ed2c0b599 daq1: Update CPLD constraints file 2016-02-12 16:54:36 +02:00
Istvan Csomortani aa2ff0223a daq1: Update CPLD design
+ SPI counter counts on negative edge of the SPI_CLK
+ Shift register for read, shifting MSB first
+ Fix write access logic
+ Update the internal register addresses
2016-02-12 14:45:18 +02:00
Istvan Csomortani c32d7147d5 daq1 : There is a single CSN from master 2016-02-12 14:38:32 +02:00
Istvan Csomortani 9675df15c6 daq1_zc706: Update constraints file 2016-02-12 14:37:02 +02:00
Istvan Csomortani e381d5170c util_tdd_sync: Update the synchronization interface
Simplify the synchronization interface, there is one signal line between the synchronization module and transceiver core.
2016-02-12 14:27:37 +02:00
Adrian Costina 61f9f72a75 fmcjesdadc1: Updated VC707 project for maximum throughput from DMA to DDR
- Increased the DMAs internal FIFO
2016-02-09 12:30:56 +02:00
Adrian Costina c431adb793 fmcjesdadc1: Updated KC705 project for maximum throughput from DMA to DDR
- Increased the DMA internal FIFO
2016-02-09 12:00:27 +02:00
Adrian Costina ad9ecbbbb6 daq2: Updated a10gx project to quartus 15.1.1 2016-02-05 17:43:05 +02:00
Istvan Csomortani a74e2061e9 ad7616_sdz: BUSY is input for the FPGA 2016-02-03 14:12:00 +02:00
Rejeesh Kutty bb62f6d225 pzsdr1- updates 2016-02-02 12:34:09 -05:00
Rejeesh Kutty 41b6ebeeaf pzsdr1- updates 2016-02-02 12:33:55 -05:00
Rejeesh Kutty b147e9c94a pzsdr1- updates 2016-02-02 12:33:01 -05:00
Istvan Csomortani 59783f6cff ad7616_sdz: Add support for Zedboard 2016-01-29 15:28:06 +02:00
Istvan Csomortani 122667259f ad7616_sdz: Update Make file 2016-01-28 14:48:44 +02:00
Istvan Csomortani 118577f64f ad7616_sdz: Add support for parallel interface 2016-01-28 12:38:22 +02:00
Rejeesh Kutty 170295161f pzsdr1- xdc 2016-01-26 11:19:00 -05:00
Istvan Csomortani cd43ebd8bc axi_ad7616: The OP_MODE parameter is no longer required 2016-01-26 11:05:33 +02:00
Rejeesh Kutty bcac3eef4d pzsdr1- initial commit 2016-01-25 16:07:33 -05:00
Rejeesh Kutty 44a382fc69 pzsdr1-added 2016-01-25 15:33:34 -05:00
Istvan Csomortani 2a17ce275c axi_ad7616: Control inputs are controlled through GPIO
The following control inputs are controlled through GPIO: reset_n, seq_en, hw_rngsel, chsel, crcen, burst and os.
2016-01-25 17:50:50 +02:00
Istvan Csomortani e22d5d5c18 daq2: Fix clock constraints for KC705 and VC707 2016-01-22 19:09:57 +02:00
Adrian Costina 59fbd99fdb fmcjesdadc1: Added clock constraint for the ADC path 2016-01-22 15:46:20 +02:00
Adrian Costina dca39c26f9 ad6676evb: Added clock constraint for the ADC path 2016-01-22 15:45:16 +02:00
Adrian Costina 9cd0378003 fmcadc2: Added clock constraint for the ADC path 2016-01-22 15:44:04 +02:00
Istvan Csomortani aa77af6bdf daq1_cpld: Add ISE project file
This file, along with the project source files, is sufficient to open and implement in ISE Project Navigator.
2016-01-21 18:05:59 +02:00
Istvan Csomortani 14f7027793 ad7616_sdz: Move the context switching to system_project.tcl 2016-01-19 11:34:28 +02:00
Istvan Csomortani 8c69c9d2ce daq1_zc706 : Update the project
+ Add AD9684 to the block design
+ Update the IO definitions
+ Update the CPLD design
+ Add 3wire SPI logic
2016-01-19 11:20:35 +02:00
István Csomortáni ab99c4456a ad9434_fmc: Delete unnecessary set_property call
HPx interface is activated by the ad_mem_hpx_interconnect process
2016-01-14 15:41:23 +02:00
Lars-Peter Clausen c094ab8b52 cn0363: Add support for the MicroZed
Add support for connecting the CN0363 to the MicroZed. This works in
combination with the MicroZed Arduino carrier board. The CN0363 needs to be
connected to the PLPMOD header.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2016-01-13 20:32:26 +01:00
Lars-Peter Clausen 514eb68876 cn0363: Factor out common parts
Factor out the common parts of the cn0363 design so we can use it to add
support for other carriers.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2016-01-13 20:32:26 +01:00
Lars-Peter Clausen d2b26720e6 common: microzed: Add clock, reset and interrupt support
In order for the base project to be usable by other projects it needs to
create the clock, reset and interrupt signals that are expected to exist.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2016-01-13 20:32:26 +01:00
Lars-Peter Clausen 51d20b1a61 adi_project.tcl: Add MicroZed support
Handle the projects for the MicroZed and set up the FPGA part accordingly.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2016-01-13 20:32:26 +01:00
Lars-Peter Clausen 426490c394 common: Rename uzed to microzed
Everybody calls the MicroZed microzed in their projects. Don't deviate from
that to avoid potential confusion.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2016-01-13 20:18:57 +01:00
Rejeesh Kutty c397787001 uzed: updates 2016-01-11 15:36:01 -05:00
Rejeesh Kutty a610ebb413 uzed: zed-copy 2016-01-11 13:53:22 -05:00
Istvan Csomortani 02cc926275 daq1: Add CPLD logic and IO constraints 2016-01-04 18:10:46 +02:00
Adrian Costina 7013b319b0 motcon2_fmc: Fixed reset connection for cpack cores 2015-12-22 12:03:34 +02:00
Istvan Csomortani 17e7d1b86f ad7616: Add Makefiles 2015-12-21 17:09:42 +02:00
Rejeesh Kutty 2bb19be3d3 pzsdr/ccfmc: sfp io control 2015-12-17 16:18:06 -05:00
Rejeesh Kutty f3fe16a102 pzsdr/ccfmc: camera/sfp pin changes 2015-12-17 16:17:24 -05:00
Rejeesh Kutty ea045a3f9a fmcadc4: change qpll to receive 2015-12-17 12:34:47 -05:00
Rejeesh Kutty 40ab2f5e6a ccfmc: tdd/gpio bit moved to the top 2015-12-17 11:37:57 -05:00
Adrian Costina 34b832e22a fmcomms6: Fixed reset connection for cpack core 2015-12-16 10:36:33 +02:00
Adrian Costina 35f6bd16e9 fmcomms5: Fixed reset connection for cpack core 2015-12-16 10:34:36 +02:00
Rejeesh Kutty 83fd4a53a7 daq3/kcu105: updates 2015-12-14 09:29:48 -05:00
Rejeesh Kutty 07316a905e daq3/a10gx: sysref is lvds 2015-12-14 09:29:10 -05:00
Istvan Csomortani ee4d5af12e ad7616_sdz: Update the project
+ Fix system_top.v
+ Finish up the common block design
+ Fix system_project.tcl
2015-12-14 16:02:38 +02:00
Istvan Csomortani f4e3523390 ad7616_sdz: Update IO constraints 2015-12-14 15:34:56 +02:00
Rejeesh Kutty 6a9d1c431a daq3/a10gx: updated to a10gx/quartus 2015-12-11 12:49:25 -05:00
Rejeesh Kutty da2e1bdc9a daq2/a10gx: 32bits generic gpio 2015-12-11 11:50:26 -05:00
Rejeesh Kutty 650d426301 a10gx/base: set gpio to 32 2015-12-11 10:14:37 -05:00
Rejeesh Kutty dc84a9ad82 daq3/a10gx: updates 2015-12-10 16:06:14 -05:00
Rejeesh Kutty f1b6577447 a10gx/base: separate gpio in/out 2015-12-10 16:04:54 -05:00
Rejeesh Kutty d944198212 daq3/a10gx: board updates 2015-12-10 09:45:20 -05:00
Rejeesh Kutty 1a38ea205d daq3/a10gx: copy 2015-12-10 09:42:56 -05:00
Rejeesh Kutty 614babc18e daq3/kcu105: copy 2015-12-10 09:41:47 -05:00
Rejeesh Kutty b0fef1122e daq3/a10gx: copy 2015-12-10 09:41:37 -05:00
Rejeesh Kutty be075379df hdlmake: updates 2015-12-07 13:11:24 -05:00
Rejeesh Kutty 0938041d97 ad7768evb: added 2015-12-07 13:07:03 -05:00
Adrian Costina 6e549171f0 fmcomms5: Connected the clk input of the ad9361 to l_clk 2015-12-02 14:43:44 +02:00
Adrian Costina 2309c4d83c Makefiles: Removed " from path 2015-11-27 14:02:46 +02:00
Adrian Costina 159f6c1216 Makefiles: Updated Makefiles
- for altera projects, taken into consideration of the new location for common qsys files
- for fmcomms5, added wfifo dependency
- for daq3, added mfifo dependency
2015-11-27 12:39:42 +02:00
Istvan Csomortani 36febf8591 Merge branch 'master' into dev
Conflicts:
	library/axi_ad9361/axi_ad9361_ip.tcl
	library/axi_dmac/Makefile
	library/axi_dmac/axi_dmac_constr.ttcl
	library/axi_dmac/axi_dmac_ip.tcl
	library/common/ad_tdd_control.v
	projects/daq2/common/daq2_bd.tcl
	projects/fmcjesdadc1/common/fmcjesdadc1_bd.tcl
	projects/fmcomms2/zc706pr/system_project.tcl
	projects/fmcomms2/zc706pr/system_top.v
	projects/usdrx1/common/usdrx1_bd.tcl

This merge was made, to recover any forgotten fixes from master,
before creating the new release branch. All conflicts were reviewed
and resolved.
2015-11-26 13:38:11 +02:00
Adrian Costina ea57b3c03c daq2: A10GX, add project specific IP search paths 2015-11-25 10:58:36 +02:00
Adrian Costina e8a595b81e fmcjesdadc1: Updated a5soc design 2015-11-24 15:39:52 +02:00
Adrian Costina fd3910a915 fmcjesdadc1: Updated a5gt design 2015-11-24 15:39:21 +02:00
Adrian Costina 9281eb2c33 fmcjesdadc1: Updated common altera design 2015-11-24 15:38:58 +02:00
Adrian Costina a81625e1fa daq2: Updated a10gx project 2015-11-24 13:28:53 +02:00
Adrian Costina 605a0768e0 arradio: Updated c5soc project 2015-11-24 13:27:44 +02:00
Adrian Costina a0e67aad56 c5soc: Updated common design 2015-11-24 13:22:01 +02:00
Istvan Csomortani c051a578e5 fmcomms2: Delete unnecessary clock definition
The two clocks, rx_clk and ad9361_clk, are the same.
2015-11-20 19:35:37 +02:00
Rejeesh Kutty c15c82d9d1 ccpci- remove ps7 ddr hp0 access 2015-11-19 16:42:02 -05:00
Rejeesh Kutty 4603bd222b ccpci- set pcie io after ip 2015-11-19 16:42:01 -05:00
Rejeesh Kutty 95af462409 ccpci- loc by pin-name is ignored 2015-11-19 16:42:00 -05:00
Rejeesh Kutty 0f8d427aef ccpci- remove ila 2015-11-19 16:41:58 -05:00
Rejeesh Kutty 9cfbf0ea61 ccpci- add axi spi/gpio 2015-11-19 16:41:57 -05:00
Rejeesh Kutty a1601a03d6 pzsdr: added ad9361 clock out 2015-11-16 15:55:56 -05:00
Rejeesh Kutty 8aefe569b8 pzsdr: output ad9361 clock out to fan io 2015-11-16 15:54:30 -05:00
Rejeesh Kutty 597e9eae84 pzsdr: added ad9361 clock out 2015-11-16 15:53:29 -05:00
Rejeesh Kutty a6f44949d6 daq3: updates 2015-11-13 13:17:11 -05:00
Adrian Costina c88cbf78af fmcomms5: Added wfifo at the between AD9361 and cpack core 2015-11-13 15:50:32 +02:00
Istvan Csomortani bec4c8da84 pzsdr: Update Make files 2015-11-11 11:16:05 +02:00
Istvan Csomortani 2345d29663 fmcomms2: Update make files 2015-11-11 11:15:45 +02:00
Istvan Csomortani a936ad607f fmcomms2/zc706: Delete unused files from file list 2015-11-11 11:14:58 +02:00
Istvan Csomortani c7e86528d6 fmcomms2/zc706: Cosmetic changes on constraints file 2015-11-11 11:14:16 +02:00
Istvan Csomortani 6197a82c80 fmcomms2/common: Add the util_tdd_sync module 2015-11-11 11:07:15 +02:00
Adrian Costina 5cc97c78d3 Makefiles: Update makefiles to include the nerw axi_gpreg / util_mfifo libraries 2015-11-10 09:32:50 +02:00
Istvan Csomortani ef9bdf6ec9 adi_project: Regenerate the layout of the IP Integrator subsystem design. 2015-11-09 11:01:10 +02:00
Istvan Csomortani 214adbfd85 ad7616_sdz_zc706: Add board related IO's to system top. 2015-11-09 10:51:46 +02:00
Rejeesh Kutty 1d6254fdec pzsdr/ccbrk: loopback board support 2015-11-06 11:34:21 -05:00
Adrian Costina afc4274ee3 common scripts: Changed the resulting hdf file to system_top_bad_timing, if design doesn't meet timing. 2015-11-06 16:01:19 +02:00
Adrian Costina 0c7c0f2cd8 common scripts: Change the name of the generated HDF if the design doesn't meet timing 2015-11-05 18:41:51 +02:00
Rejeesh Kutty 11718291cf pzsdr/ccfmc- add single loopback core 2015-11-05 11:28:38 -05:00
Rejeesh Kutty 9e27a60478 pzsdr/ccfmc- single loopback core 2015-11-05 11:28:33 -05:00
Adrian Costina e36f27b061 daq2: Update A10GX project, with the latest changes.
Works with up to 64k samples
2015-11-04 14:54:09 +02:00
Adrian Costina 83399ef6ee a10gx: Updated common project to work with Linux (enabled MMU) 2015-11-04 13:35:52 +02:00
Istvan Csomortani 27266c59ee ad7616_sdz: Add project source files 2015-11-03 15:03:35 +02:00
Lars-Peter Clausen a0039ed4fe ccfmc: Launch HDMI data on falling edge
The ADV7511 captures data on the rising edge, so make sure to launch data
on the falling edge. This fixes some issues with image stability.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-11-03 10:59:13 +01:00
Rejeesh Kutty 6dddac5d94 ccfmc- missing board io 2015-11-02 15:45:14 -05:00
Rejeesh Kutty cafc80c829 fmcadc5: add programmable io delay 2015-11-02 12:10:18 -05:00
Rejeesh Kutty 8b95520767 pzsdr/ccfmc- add loopback gpio/gt cores 2015-10-30 18:48:26 -04:00
Rejeesh Kutty 92b7570864 pzsdr/ccfmc- add ad9517 signals 2015-10-30 10:50:53 -04:00
Rejeesh Kutty b3cb84cf91 fmcadc5- added ila 2015-10-29 16:48:21 -04:00
Rejeesh Kutty 24d76c610a fmcadc5- fix core connections 2015-10-29 16:47:56 -04:00
Rejeesh Kutty ac4091e19e fmcadc4- add monitor fifo 2015-10-27 14:52:02 -04:00
Adrian Costina b5d3d0bd13 usb_fx3: Added axi_usb_fx3 core and DMA to the project 2015-10-27 09:41:18 +02:00
Rejeesh Kutty 748a2bc87a fmcadc4- add ila for zc706 only 2015-10-23 14:32:35 -04:00
Rejeesh Kutty b2d0f5c56e fmcadc4- use the same source/name for clocks 2015-10-23 14:32:35 -04:00
Adrian Costina 9d2b8809df Makefiles: Updated Makefiles 2015-10-23 10:44:27 +03:00
Rejeesh Kutty cb2bda48c0 fmcadc5- gt/ip updates 2015-10-19 09:31:32 -04:00
Rejeesh Kutty ed918ec119 imageon - keeping scripts happy 2015-10-16 15:04:02 -04:00
Rejeesh Kutty e14e9294c5 project-names -- variables causes scripts to fail- too much parsing 2015-10-16 14:13:56 -04:00
Istvan Csomortani 36dd6427fe pzsdr: Add untracked Makefiles 2015-10-16 13:58:36 +03:00
Istvan Csomortani bbdc693954 pzsdr/all: Update Makefile 2015-10-16 11:57:51 +03:00
Rejeesh Kutty 08777ca566 fmcadc5- latest board changes 2015-10-15 10:46:07 -04:00
Rejeesh Kutty 030485de28 fmcadc5- regulators need a switching ref clock? 2015-10-15 10:46:07 -04:00
Rejeesh Kutty f966f79e5f fmcadc5- regulators need a switching ref clock? 2015-10-15 10:46:07 -04:00
Nicholas Pillitteri 199227b78c fix fmcjesdadc1_bd ILA warning 2015-10-13 10:19:08 -04:00
Istvan Csomortani 21737ad7b8 fmcomms2/zc706pr: Update the fifo interface of the PR module 2015-10-13 11:37:44 +03:00
Istvan Csomortani c9a5057b93 library/prcfg : Split data bus to channels
Because of the new pack/upack modules on the data path, it makes more sense to split the data interface of the PR modules into separate channels.
The top module will supports max 4 channels.
2015-10-13 11:36:45 +03:00
Adrian Costina 9bb70e2b69 motcon2_fmc: Updated ZED project 2015-10-09 15:33:31 +03:00
Adrian Costina 83fb5c742a motcon2_fmc: Updated project to Vivado 2015.2.1
- added cpack cores
- removed controller DMA paths
2015-10-09 13:56:41 +03:00
Adrian Costina 88e8bef92f usdrx1: Update ZC706 project 2015-10-09 13:33:45 +03:00
Adrian Costina 02c0a5f5df usdrx1: Update project to Vivado 2015.2.1 2015-10-09 13:33:07 +03:00
Istvan Csomortani c83239b014 fmcomms2/zc706pr: Update PR design
+ Add system_top.v to design
+ Add pr specific constraints
2015-10-09 13:23:42 +03:00
Istvan Csomortani 09be227db9 fmcomms2/zc706pr: Update PR design
+ Add system_top.v to design
+ Add pr specific constraints
2015-10-09 13:19:09 +03:00
Istvan Csomortani e4517c0d6a daq2/common: Connect reset to dac fifo 2015-10-08 16:51:08 +03:00
Adrian Costina df88b33946 usb_fx3: Initial commit
Only the UART connections are available.
The FMC should not be populated at this time
2015-10-02 09:30:31 +03:00
Rejeesh Kutty b93af3c21e daq3- bd updates 2015-09-30 10:11:49 -04:00
Istvan Csomortani 81a1c21553 util_pmod_adc: Reset line changed to active low reset. 2015-09-30 12:33:46 +03:00
Istvan Csomortani 5f12c8c7d4 cftl_cip/common: Fix parameter names for dmac 2015-09-30 12:32:48 +03:00
Istvan Csomortani 3dc881dbb3 pmods/xfest14: Delete directory
This project will not be supported from the next release
2015-09-30 12:25:31 +03:00
Istvan Csomortani e6af671bea cn0363/zed: Fix DMAC parameter names 2015-09-30 11:31:53 +03:00
Istvan Csomortani 4aa4ffc25f imageon/common: Update cores to Vivado 2015.2 2015-09-29 18:51:46 +03:00
Istvan Csomortani e60d2f86b3 imageon/common: Fix parameter name for spdif_rx 2015-09-29 18:50:41 +03:00
Istvan Csomortani b4252a8512 imageon_loopback: Delete directory
This project will not be supported from the next releases.
2015-09-29 14:53:44 +03:00
Adrian Costina 9832cea071 ad9739a_fmc: Common, reduced DMA fifo size 2015-09-28 12:19:23 +03:00
Adrian Costina 5b48340b08 fmcomms6: Updated ZC706 project 2015-09-28 11:32:20 +03:00
Adrian Costina 3b3c645827 fmcomms6: Updated project to Vivado 2015.2.1. Added cpack 2015-09-28 11:31:08 +03:00
Istvan Csomortani 046c89dacd fmcomms2/pr: Delete the fmcomms2_pr directory
The fmcomms2/pr project is moved to fmcomms2/zc706pr
2015-09-25 19:11:43 +03:00
Istvan Csomortani f77f928444 fmcomms2/zed: Fix the system_top
Fix the enable/txnrx control line.
2015-09-25 19:11:41 +03:00
Istvan Csomortani aeb1d7aa3e fmcomms2/zed: Cosmetic changes 2015-09-25 19:11:39 +03:00
Istvan Csomortani f8b3096bd0 fmcomms2/vc707: Fix the system_top
Fix the enable/txnrx control lines.
2015-09-25 19:11:37 +03:00
Istvan Csomortani 2c75cfd04e fmcomms2/vc707: Cosmetic changes 2015-09-25 19:11:35 +03:00
Istvan Csomortani ffa0bcd19f fmcomms2/mitx045: Fix the system_top
Fix the enable/txnrx control lines.
2015-09-25 19:11:32 +03:00
Istvan Csomortani 28d20e84c5 fmcomms2/zc702: Fix the system_top
Fix the enable/txnrx control lines.
2015-09-25 19:11:30 +03:00
Istvan Csomortani ea74413125 fmcomms2/kc705: Fix the system_top.
Fix the enable/txnrx control lines.
2015-09-25 19:11:28 +03:00
Istvan Csomortani f80622b972 fmcomms2/ac701: Fix the system_top
Fix the enable/txnrx control line.
2015-09-25 19:11:26 +03:00
Istvan Csomortani 07e2d281c0 Make: Update Make files 2015-09-25 19:11:21 +03:00
Istvan Csomortani 1604e88242 fmcadc4: Update project to the new JESD interface framework 2015-09-25 19:11:19 +03:00
Istvan Csomortani f4b432da08 fmcadc4: Update to 2015.2 2015-09-25 19:11:17 +03:00
Istvan Csomortani 4f99bdd93f fmcadc5: Update project
+ Update the JESD IP core for Vivado 2015.2
+ Update the framework for JESD interface
2015-09-25 19:11:14 +03:00
Istvan Csomortani f5b5bbfbca fmcomms7: Update to the new JESD framework
Update project to the new framework for JESD interface and add a DAC FIFO to the transmit path.
2015-09-25 19:11:12 +03:00
Istvan Csomortani fbd51c2734 fmcomms7: Update to 2015.2
Update IP core version of jesd204.
2015-09-25 19:11:10 +03:00
Adrian Costina d198caa621 fmcomms2: Updated ZC702 design 2015-09-25 18:15:40 +03:00
Istvan Csomortani 4b115fbe69 ad9467_fmc: Delete ILA from the design 2015-09-25 17:41:46 +03:00
Adrian Costina 7853843036 fmcomms5: Update ZC706 project 2015-09-25 17:32:29 +03:00
Adrian Costina 108ffebae4 fmcomms5: Updated project to 2015.2.1
- added cpack / upack
2015-09-25 17:31:08 +03:00
Adrian Costina 848b51699c fmcadc2: Updated VC707 project 2015-09-25 17:28:15 +03:00
Adrian Costina e764f54426 fmcadc2: Updated ZC706 project 2015-09-25 17:26:54 +03:00
Adrian Costina 6fbd8dd9a5 fmcadc2: Update projecct to 2015.2.1
- updated to the new jesd framework
2015-09-25 17:25:32 +03:00
Adrian Costina ab4b73fd32 ad6676evb: Updated VC707 project 2015-09-25 16:07:22 +03:00
Adrian Costina 33390c85f8 ad6676evb: Update ZC706 project 2015-09-25 14:46:02 +03:00
Adrian Costina a49230ec07 ad6676evb: Updated project to 2015.2.1
- updated to the new jesd framework
- added cpack core
2015-09-25 14:44:46 +03:00
Adrian Costina 7f9c526683 fmcjesdadc1: VC707 update project 2015-09-24 19:50:14 +03:00
Adrian Costina 78fe05120b fmcjesdadc1: Updated KC705 project 2015-09-24 19:14:48 +03:00
Adrian Costina 70c7c2aeb8 fmcjesdadc1: Updated ZC706 project 2015-09-24 19:14:05 +03:00
Adrian Costina 2ed161628d fmcjesdadc1: Updated project to 2015.2.1
- updated to the new jesd framework
- added cpack core
2015-09-24 19:12:40 +03:00
Adrian Costina 58ab70bc0e fmcomms1: Update AC701 project
Renamed mdio pin, as it's exported by the system wrapper
Renamed DMA parameter
2015-09-24 19:07:19 +03:00
Rejeesh Kutty f9801e8c85 pzsdr/cc*- rf card on fmc only 2015-09-23 09:16:41 -04:00
Rejeesh Kutty 9832ea95a8 pzsdr/ccpci- initial version 2015-09-22 16:30:27 -04:00
Rejeesh Kutty 14bccb6062 pzsdr/ccfmc- rf card/tdd only on fmc 2015-09-22 15:54:53 -04:00
Rejeesh Kutty fa5d879fdb pzsdr/ccpci -- updates 2015-09-21 14:54:31 -04:00